EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 796

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Quartus II Software Support
12–18
Stratix Device Handbook, Volume 2
<rublock_name>
.clk(<clock source>)
.shiftnld(<shiftnld source>)
.captnupdt(<shiftnld
source>)
.regin(<regin input source
from the core>)
.rsttimer(<input signal to
reset the watchdog timer>)
.config(<input signal to
initiate configuration>)
.regout(<data output
destination to core>)
.pgmout(<program output
destinations to pins>)
Table 12–9. Remote Update Block Input & Output Ports
Ports
The Stratix and Stratix GX remote update atom ports are:
Stratix_rublock <rublock_name>
(
Table 12–9
and descriptions.
The unique identifier for the instance. This identifier name can be anything as
long as it is legal for the given description language (i.e., Verilog, VHDL, AHDL,
etc.). This field is required.
Designates the clock input of this cell. All operation is with respect to the rising
edge of this clock. This field is required.
An input into the remote configuration block. When .shiftnld = 1, the data shifts
from the internal shift registers to the
and the data also shifts into the internal shift registers from
is required.
An input into the remote configuration block. This controls the protocol of when
to read the configuration mode or when to write into the registers that control the
configuration. This field is required.
An input into the configuration block for all data loading into the core. The data
shifts into the internal registers at the rising edge of
An input into the watchdog timer of the remote update block. When this is high, it
resets the watchdog timer. This field is required.
An input into the configuration section of the remote update block. When this
signal goes high, the part initiates a re-configuration. This field is required.
A 1-bit output, which is the output of the internal shift register, and updated every
rising edge of
field is required.
A 3-bit bus. It should always be connected only to output pins (not
This bus gives the page address (
loaded when the device is getting configured. This field is required.
.clk(<clock source>),
.shiftnld(<shiftnld source>),
.captnupdt(<shiftnld source>),
.regin(<regin input source from the core>),
.rsttimer(<input signal to reset the watchdog timer>),
.config(<input signal to initiate configuration>),
.regout(<data output destination to core>),
.pgmout(<program output destinations to pins>)
shows the remote update block input and output port names
clk
. The data coming out depends on the control signals. This
000
Definition
regout
to
111
) of the configuration data to be
port at each rising edge of
clk
. This field is required.
regin
Altera Corporation
September 2004
port. This field
bidir
clk
pins).
,