EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 300

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Contents
Chapter 7. Implementing High Performance DSP Functions
in Stratix & Stratix GX Devices
Section V. IP & Design Considerations
viii
Operational Modes .............................................................................................................................. 6–18
Software Support ................................................................................................................................. 6–28
Conclusion ............................................................................................................................................ 6–28
Introduction ............................................................................................................................................ 7–1
Stratix & Stratix GX DSP Block Overview ......................................................................................... 7–1
TriMatrix Memory Overview .............................................................................................................. 7–4
DSP Function Overview ....................................................................................................................... 7–5
Finite Impulse Response (FIR) Filters ................................................................................................. 7–5
Infinite Impulse Response (IIR) Filters ............................................................................................. 7–34
Matrix Manipulation ........................................................................................................................... 7–45
Discrete Cosine Transform (DCT) ..................................................................................................... 7–52
Arithmetic Functions ........................................................................................................................... 7–59
Conclusion ............................................................................................................................................ 7–62
References ............................................................................................................................................. 7–63
Revision History ..................................................................................................................... Section V–1
Multiplier Block ................................................................................................................................ 6–5
Adder/Output Block ....................................................................................................................... 6–9
Routing Structure & Control Signals ........................................................................................... 6–12
Simple Multiplier Mode ................................................................................................................ 6–18
Multiply Accumulator Mode ........................................................................................................ 6–22
Two-Multiplier Adder Mode ........................................................................................................ 6–23
Four-Multiplier Adder Mode ....................................................................................................... 6–24
FIR Filter Background ...................................................................................................................... 7–6
Basic FIR Filter .................................................................................................................................. 7–7
Time-Domain Multiplexed FIR Filters ........................................................................................ 7–13
Polyphase FIR Interpolation Filters ............................................................................................. 7–17
Polyphase FIR Decimation Filters ................................................................................................ 7–24
Complex FIR Filter ......................................................................................................................... 7–31
IIR Filter Background .................................................................................................................... 7–34
Basic IIR Filters ............................................................................................................................... 7–36
Butterworth IIR Filters ................................................................................................................... 7–39
Background on Matrix Manipulation .......................................................................................... 7–45
Two-Dimensional Filtering & Video Imaging ........................................................................... 7–46
DCT Background ............................................................................................................................ 7–52
2-D DCT Algorithm ....................................................................................................................... 7–53
Background ..................................................................................................................................... 7–59
Arithmetic Function Implementation ......................................................................................... 7–60
Arithmetic Function Implementation Results ............................................................................ 7–62
Arithmetic Function Design Example ......................................................................................... 7–62
Stratix Device Handbook, Volume 2
Altera Corporation