EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 740

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Configuration Schemes
11–22
Stratix Device Handbook, Volume 2
FPP Configuration Using an Enhanced Configuration Device
When using FPP with an enhanced configuration device, it supplies data
in a byte-wide fashion to the Stratix or Stratix GX device every DCLK
cycle. See
Figure 11–10. FPP Configuration Using Enhanced Configuration Devices
Notes to
(1)
(2)
(3)
In the enhanced configuration device scheme, nCONFIG is tied to
nINIT_CONF. On power up, the target Stratix or Stratix GX device senses
the low-to-high transition on nCONFIG and initiates configuration. The
target Stratix or Stratix GX device then drives the open-drain CONF_DONE
pin low, which in-turn drives the enhanced configuration device’s nCS
pin low.
Before configuration starts, there is a 2-ms POR delay if the PORSEL pin
is connected to V
pin is connected to ground, the POR delay is 100 ms. When each device
determines that its power is stable, it releases its nSTATUS or OE pin.
Because the enhanced configuration device’s OE pin is connected to the
target Stratix or Stratix GX device’s nSTATUS pin, configuration is
delayed until both the nSTATUS and OE pins are released by each device.
The nSTATUS and OE pins are pulled up by a resistor on their respective
The pull-up resistors should be connected to the same supply voltage as the
configuration device.
The enhanced configuration devices and EPC2 devices have internal
programmable pull-ups on OE and nCS. You should only use the internal pull-ups
of the configuration device if the nSTATUS and CONF_DONE signals are pulled up
to 3.3 V or 2.5 V (not 1.8 V or 1.5 V). If external pull-ups are used, they should be
10 k
The nINIT_CONF pin is available on EPC16, EPC8, EPC4, and EPC2 devices. If
nINIT_CONF is not used, nCONFIG must be pulled to V
nINIT_CONF pin has an internal pull-up resistor that is always active in EPC16,
EPC8, EPC4, and EPC2 devices. These devices do not need an external pull-up
resistor on the nINIT_CONF pin.
GND
Figure
Figure
MSEL2
MSEL1
MSEL0
Stratix GX Device
11–10:
Stratix or
CC
11–10.
CONF_DONE
in the enhanced configuration device. If the PORSEL
DATA[7..0]
nCONFIG
nSTATUS
nCEO
DCLK
nCE
N.C.
GND
V
CC
10 kΩ
(1)
(2)
V
CC
10 kΩ
(1)
(2)
CC
through a resistor. The
DCLK
DATA[7..0]
OE (2)
nCS (2)
nINIT_CONF (3)
Altera Corporation
Configuration
Enhanced
Device
July 2005