EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 426

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

I/O Standards
Section III–2
Chapter
September 2004,
November 2003,
April 2004, v3.0
July 2003, v2.0
October 2003,
Date/Version
v3.1
v2.2
v2.1
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Table 4–1 on page
added Note 1.
Deleted Figure named “1.5-V Differential HSTL Class II
Termination.”
Updated text describing
Preliminary Standard JC42.3” on page
Updated HyperTransport data rates on
Changed HyperTransport device speed from 800 MHz to
400 MHz on
Added four rows to
V HSTL Class I, 1.8-V HSTL Class I, 1.5-V HSTL Class II,
and 1.8-V HSTL Class II.
Changed title of
Updated
Updated
Added description of which clock pins support differential
on-chip termination on
Updated description of flip-chip packages on
Changed title of
Updated milliamps for non-thermally enhanced cavity up
and non-thermally enhanced FineLine BGA packages on
page
Updated equation for FineLine BGA package on
page
Updated milliamps in non-thermally enhanced cavity up and
non-thermally enhanced FineLine BGA packages
onpage
Updated notes to
New information added to the
New information added to the
Guidelines”
Removed support for series and parallel on-chip
termination.
Updated
Added the Output Enable Group Logic Option in Quartus II
and Toggle Rate Logic Option in Quartus II sections.
Updated notes to
Renamed impedance matching to series termination
throughout Chapter.
Removed wide range specs for LVTTL and LVCMOS
standards pages 4-3 to 4-5.
Relaxed restriction of input pins next to differential pins for
flipchip packages (pages 4-20, 4-35, and 4-36).
Added Drive Strength section on page 4-26.
Removed text “for 10 ns or less” from AC Hot socketing
specification on page 4-27.
Added Series Termination column to Table 4-9.
4–35.
4–35.
4–37.
Table 4–4 on page
Figure 4–20 on page
Figure
section.
page
4–22.
Table 4–3 on page
Figure 4–21 on page
Figure
Table
4–17.
4–1: renamed table, updated table, and
Table 4–2 on page
Changes Made
page
4–10.
“SSTL-18 Class I & II - EIA/JEDEC
4–18.
4–22.
4–30.
“Hot Socketing”
“Differential Pad Placement
4–29.
4–21.
4–31.
4–18: 1.5-
4–11.
page
Stratix Device Handbook, Volume 2
4–17.
page
section.
4–31.
Altera Corporation
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