EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 524

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Software Support
5–52
Stratix Device Handbook, Volume 2
f
Stratix devices can drive the PLL_LOCK signal to both output pins and
internal logic. As a result, you do not need a dedicated LOCK pin for your
PLLs. In addition, there is only one PLL_ENABLE pin that enables all the
PLLs on the device, including the fast PLLs. You must use either the
LVTTL or LVCMOS I/O standard with this pin.
Table 5–9
Fast PLLs
Each fast PLL features a multiplexed input path from a global or regional
clock net. A clock pin or an output from another PLL in the device can
drive the input path. The input clock for PLLs used to clock receiver the
rx_inclock port on the altlvds_rx megafunction must be driven by
a dedicated clock pin (CLK[3..0,8..11]) or the corner pins that clock the
corner PLLs (FPLL[10..7]CLK). EP1S10, EP1S20, and EP1S25 devices have
a total of four fast PLLs located in the center of both sides of the device
(see
additional fast PLLs per side at the top and bottom corners of the device.
As shown in
bank with the closest center fast PLL (e.g., PLLs 1 and 7 share an I/O
bank). The maximum input clock frequency for enhanced PLLs is 684
MHz and 717 MHz for fast PLLs.
For more information on Stratix PLLs, see the General-Purpose PLLs in
Stratix & Stratix GX Devices chapter.
Notes to
(1)
(2)
DIFFIO_TX#p
DIFFIO_TX#n
DIFFIO_RX#p
DIFFIO_RX#n
FPLLCLK#p
FPLLCLK#n
CLK#p
CLK#n
Table 5–9. LVDS Pin Names
Figure 5–16 on page
The FPLLCLK pin-pair is only available in EP1S30, EP1S40, EP1S60, EP1S80
devices.
Either a FPLLCLK pin or a CLK pin can drive the corner fast PLLs (PLL7, PLL8,
PLL9, and PLL10) when used for general purpose. CLK pins cannot drive these
fast PLLs in high-speed differential I/O mode.
Pin Names
Table
displays the LVDS pins in Stratix devices.
Figure 5–17 on page
5–9:
Transmitter positive data or output clock pin
Transmitter negative data or output clock pin
Receiver positive data pin
Receiver negative data pin
Positive input clock pin to the corner fast PLLs (1),
Negative input clock pin to the corner fast PLLs (1),
Positive input clock pin
Negative input clock pin
5–23). EP1S30 and larger devices have two
5–24, the corner fast PLL shares an I/O
Functions
(2)
(2)
Altera Corporation
July 2005
(2)
(2)