EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 749

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 11–16. PPA Configuration Circuit
Note to
(1)
Altera Corporation
July 2005
The pull-up resistor should be connected to the same supply voltage as the Stratix or Stratix GX device.
Figure
ADDR
Address Decoder
11–16:
ADDR DATA[7..0]
Memory
Microprocessor
Figure 11–16
decoder controls the device’s nCS and CS pins. This decoder allows the
microprocessor to select the Stratix or Stratix GX device by accessing a
particular address, simplifying the configuration process.
The device’s nCS or CS pins can be toggled during PPA configuration if
the design meets the specifications for t
Table 11–10 on page
the nCS and CS signals. You can tie one of the nCS or CS signals to its
active state (i.e., nCS may be tied low) and toggle the other signal to
control configuration.
Stratix and Stratix GX devices can serialize data internally without the
microprocessor. When the Stratix or Stratix GX device is ready for the
next byte of configuration data, it drives RDYnBSY high. If the
microprocessor senses a high signal when it polls RDYnBSY, the
microprocessor strobes the next byte of configuration data into the
device. Alternatively, the nRS signal can be strobed, causing the
RDYnBSY signal to appear on DATA7. Because RDYnBSY does not need to
10 kΩ
V
CC
(1)
shows the PPA configuration circuit. An optional address
10 kΩ
11–36. The microprocessor can also directly control
V
CC
V
GND
(1)
CC
10 k Ω
(1)
nCS
CS
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nWS
nRS
nCONFIG
RDYnBSY
Configuring Stratix & Stratix GX Devices
Stratix Device
Stratix Device Handbook, Volume 2
CSSU
, t
WSP
nCEO
MSEL2
MSEL1
MSEL0
DCLK
, and t
CSH
N.C.
V
CC
GND
given in
(1)
10 kΩ
V
CC
11–31