EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 585

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
September 2004
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Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Basic FIR Filter
A basic FIR filter is the simplest FIR filter type. As shown in
basic FIR filter has a single input channel and a single output channel.
Basic FIR Filter Implementation
Stratix and Stratix GX devices’ dedicated DSP blocks can implement basic
FIR filters. Because these DSP blocks have closely integrated multipliers
and adders, filters can be implemented with minimal routing resources
and delays. For implementing FIR filters, the DSP blocks are configured
in the four-multipliers adder mode.
See the DSP Blocks in Stratix & Stratix GX Devices chapter for more
information on the different modes of the DSP blocks.
This section describes the implementation of an 18-bit 8-tap FIR filter.
Because Stratix and Stratix GX devices support modularity, cascading
two 4-tap filters can implement an 8-tap filter. Larger FIR filters can be
designed by extending this concept. Users can also increase the number
of taps available per DSP block if 18 bits of resolution are not required. For
example, by using only 9 bits of resolution for input samples and
coefficient values, 8 multipliers are available per DSP block. Therefore, a
9-bit 8-tap filter can be implemented in a single DSP block provided an
external adder is implemented in logic cells.
The four-multipliers adder mode, shown in
18
can implement a 4-tap filter. The data width of the input and the
coefficients is 18 bits, which results in a 38-bit output for a 4-tap filter.
18-bit multipliers and three adders in a single DSP block. Hence, it
Stratix Device Handbook, Volume 2
Figure
7–3, provides four
Figure
7–2, a
7–7