EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 659

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 8–11. Stratix & Stratix GX XGMII Implementation
Altera Corporation
July 2005
Stratix & Stratix GX PCS
Logic Array
Stratix GX
Stratix &
Data
Data
Clk
Clk
Receiver
Transmitter
DDR Output Circuitry
DDR Input Circuitry
For this implementation, the shift register clocks can either be generated
from a divided down MAC reconciliation sublayer transmitter clock
(MAC_TXCLK), or the asynchronous core clock, or both if using a FIFO
buffer.
Figure 8–12
transmitted from the PCS to the MAC reconciliation sublayer starts at the
core of the Stratix or Stratix GX device and travels to the shift register. The
shift register takes in the parallel data (even bits sent to the top register
and odd bits sent to the bottom register) and serializes the data. After the
data is serialized, it travels to the double data rate (DDR) output circuitry,
which is clocked with the 4 clock from the PLL. Out of the DDR output
circuitry, the data drives off-chip along with the 4 clock. This transaction
creates the DDR relationship between the clock and the data output. This
implementation only shows one channel, but can be duplicated to include
all 32 bits of the RX_D signal and all 4 bits of the RX_C signal.
PLL2
Register
Register
Shift
÷4
Shift
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
PLL1
shows one channel of the output half of XGMII. Data that is
×4
MAC_RXCLK
MAC_TXCLK
RX_D[31..0]
TX_D[31..0]
RX_C[3..0]
TX_C[3..0]
Stratix Device Handbook, Volume 2
MAC (RS)
Transmitter
Receiver
8–15