EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 718

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

System Configuration & Upgrades
Revision History
Section VI–2
Chapter
11
12
September 2004, v3.1
September 2004, v3.1
April 2004, v3.0
April 2004, v3.0
July 2005, v3.2
July 2003, v2.0
July 2003, v2.0
Date/Version
The table below shows the revision history for
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Updated
Updated
Device”
Updated
Corrected spelling error.
In the
several pull-down resistors were changed to pull-up resistors.
Updated notes in
Two vertical V
Three paragraphs added regarding the
INIT_DONE
Value in Note 1 changed in
Deleted reference to AS in
support AS mode.
Text added before callout of
Updated Remote/local update PPA typical use description on page
11-1.
Updated VCCSEL Pins section on page 11-3.
Updated figures to use 10k resistors throughout for configuration
control signals.
Updated text on page 11-23 to tell how to connect a microprocessor
to nSTATUS.
Figure
Updated
Added Note 6 to
the
Updated definitions for CLKUSR, and JTAG pins in
Editorial corrections.
The input file in
remote_update_initial_pgm.pdf.
Title in
Partial Programming File Generation.
Rearranged the
Added altremote_update Megafunction section on pages 12-18 to 12-
21.
nCE
“PORSEL Pins”
11–19, Note 3.
Figure 12–23
section.
pin.
“PORSEL Pins”
“FPP Configuration Using an Enhanced Configuration
“PPA Configuration”
Table
pins on page 13-18.
CC
11–12.
Figure 12–22
Figure 11–21
“Quartus II Software Support”
lines removed in
Figure
was changed from Local... to Remote Update
section and the
11–3.
Changes Made
and
Table 11–15
Tables 11–8
Figure
section.
“nIO_PULLUP Pins”
was changed to
and the text below the figure describing
Stratix Device Handbook, Volume 2
Figures 11–12
11–7.
“nIO_PULLUP Pins”
CONF_DONE
because Stratix does not
and 11–9.
Chapters 11
section.
to 11–14.
Altera Corporation
sections.
Table
and
through 12.
11–16.
section,