EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 486

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Using SERDES to Implement SDR
Figure 5–9. DDR Clock-to-Data Relationship
Figure 5–10. DDR Receiver & Transmitter Circuit Connection
Using SERDES
to Implement
SDR
5–14
Stratix Device Handbook, Volume 2
inclock
data rate = 800 Mbps
DDR
400 MHz
rx_d[15]
rxclk
rx_d[0]
XX
Stratix SERDES DDR Receiver
LVDS PLL
Channel
Channel
input clock × W
15
B0
0
Serial-to-Parallel
Serial-to-Parallel
Register
Register
Figure 5–9
center-aligned with respect to data.
between the receiver and transmitter circuits.
Stratix devices support systems based on single data rate (SDR)
operations applications by allowing you to directly transmit out the
multiplied clock (as described in
page
interfaces, and support various data rates.
An additional differential channel is automatically configured to produce
the transmitter clock output signal and is transmitted along with the data.
For example, when a system is required to transmit 10 Gbps with a 1-to-
1 clock-to-data ratio, program the SERDES with sixteen high-speed
channels running at 624 Mbps each. The Quartus II software
A0
rxloadena
5–12). These systems are usually based on Utopia-4, SFI-4, or XSBI
Register
Register
Parallel
Parallel
shows a DDR clock-to-data timing relationship with the clock
B1
8
8
Stratix
Logic
Array
A1
LVDS PLL
8
8
8
txloaden
Stratix SERDES DDR Transmitter
B2
“SDR Transmitter Clock Output” on
Register
Register
Register
Parallel
Parallel
Parallel
Figure 5–10
input clock × W
A2
Parallel-to-Serial
Parallel-to-Serial
Parallel-to-Serial
Register
Register
Register
shows the connection
Channel
Channel
Altera Corporation
B3
Channel
÷2
15
0
16
800 Mbps
data rate = 800 Mbps
400 MHz
100 MHz
txclk_out
txclk_out
txclk_in
tx_d[0]
July 2005
A3