EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 456
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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I/O Termination
I/O Termination
4–28
Stratix Device Handbook, Volume 2
You can power up or power down the V
sequence. The power supply ramp rates can range from 100 ns to 100 ms.
During hot socketing, the I/O pin capacitance is less than 15 pF and the
clock pin capacitance is less than 20 pF.
DC Hot Socketing Specification
The hot socketing DC specification is | I
AC Hot Socketing Specification
The hot socketing AC specification is | I
This specification takes into account the pin capacitance, but not board
trace and external loading capacitance. Additional capacitance for trace,
connector, and loading must be considered separately.
I
specification applies when all VCC supplies to the device are stable in the
powered-up or powered-down conditions. For the AC specification, the
peak current duration because of power-up transients is 10 ns or less. For
more information, refer to the Hot-Socketing & Power-Sequencing Feature &
Testing for Altera Devices white paper.
Although single-ended, non-voltage-referenced I/O standards do not
require termination, Altera recommends using external termination to
improve signal integrity where required.
The following I/O standards do not require termination:
■
■
■
■
■
■
■
■
Voltage-Referenced I/O Standards
Voltage-referenced I/O standards require both an input reference
voltage, V
board should be used for series and parallel termination.
IOPIN
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI/Compact PCI
3.3-V PCI-X 1.0
3.3-V AGP 1
is the current at any user I/O pin on the device. The DC
REF,
and a termination voltage, V
CCIO
IOPIN
IOPIN
TT
. Off-chip termination on the
and V
| < 300 A.
| < 8 mA for 10 ns or less.
CCINT
Altera Corporation
pins in any
June 2006
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