EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 564

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Architecture
Figure 6–7. DSP Row Interface Block
6–14
Stratix Device Handbook, Volume 2
C4 and C8
Interconnects
LAB
DSP Block to
LAB Row Interface
Block Interconnect Region
DirectLink Interconnect
from Adjacent LAB
10
Control Signals in the Row Interface Block
The DSP block has a set of input registers, a pipeline register, and an
output register. Each register is grouped in banks that share the same
clock and clear resources:
■
■
■
1- to 9-bit banks for the input register
1- to 18-bit banks for the pipeline register
18 bits for the output register
Row Interface
3
18
Block
18 Inputs per Row
R4 and R8 Interconnects
10
9
Control
[17..0]
DSP Block
Row Structure
[17..0]
18 Outputs per Row
Nine DirectLink Outputs
to Adjacent LABs
18
18
9
Altera Corporation
DirectLink Interconnect
from Adjacent LAB
July 2005
LAB