EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 547

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 5–48. SERDES Bypass LVDS Transmitter with Logic Array as Deserializer
Summary
Altera Corporation
July 2005
Data[7..0]
Clock
PLL
×4 clock
×1 clock
The Stratix device family of flexible, high-performance, high-density
PLDs delivers the performance and bandwidth necessary for complex
system-on-a-programmable-chip (SOPC) solutions. Stratix devices
support multiple I/O protocols to interface with other devices within the
system. Stratix devices can easily implement processing-intensive data-
path functions that are received and transmitted at high speeds. The
Stratix family of devices combines a high-performance enhanced PLD
architecture with dedicated I/O circuitry in order to provide I/O
standard performances of up to 840 Mbps.
Counter
High-Speed Differential I/O Interfaces in Stratix Devices
clock
load
data
data
load
clock
Register
Register
Shift
Shift
data_h
data_l
Stratix Device Handbook, Volume 2
Output
DDR
Serial
data out
tx_clk
5–75