EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 358

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Clocking
Figure 1–21. Global & Regional Clock Connections from Side Clock Pins & Fast PLL Outputs
Notes to
(1)
(2)
1–48
Stratix Device Handbook, Volume 2
FPLL7CLK
FPLL8CLK
The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A dedicated pin or other PLL
must drive the global or regional source. The source cannot be driven by internally generated logic before driving
the fast PLL.
PLLs 3, 4, 9, and 10 are used for the HSSI block in Stratix GX devices and are not available for this use.
CLK2
CLK3
CLK0
CLK1
Figures
1–21:
PLL 7
PLL 1
PLL 2
PLL 8
g0
g0
g0
g0
l0
l1
l0
l1
l0
l1
l0
l1
2
When using a fast PLL to compensate for clock delays to drive logic on
the chip, the clock delay from the input pin to the clock input port of the
PLL is compensated only if the clock is fed by the dedicated input pin
closest to the PLL. If the fast PLL gets its input clock from a global or
regional clock or from another dedicated clock pin, which does not
directly feed the fast PLL, the clock signal is first routed onto a global
clock network. The signal then drives into the PLL. In this case, the clock
delay is not fully compensated and the delay compensation is equal to the
clock delay from the dedicated clock pin closest to the PLL to the clock
input port of the PLL.
For example, if you use CLK0 to feed PLL 7, the input clock path delay is
not fully compensated, but if FPLL7CLK feeds PLL 7, the input clock path
delay is fully compensated.
Figure 1–22
connections from the fast PLLs.
information as
each specific PLL output port drives to.
Regional
Clocks
shows the global and regional clock input and output
Tables 1–15
Clocks
Global
and
1–16
Figure 1–22
Regional
Clocks
but with the added detail of where
shows graphically the same
2
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0
PLL 10
PLL 4
PLL 3
PLL 9
Altera Corporation
July 2005
FPLL10CLK
CLK10
CLK11
CLK8
CLK9
FPLL9CLK