MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 80
MC68302EH20C
Manufacturer Part Number
MC68302EH20C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH20C.pdf
(481 pages)
Specifications of MC68302EH20C
Processor Type
M683xx 32-Bit
Speed
20MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
20MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH20C PDF datasheet #4
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System Integration Block (SIB)
When acting as a general-purpose I/O pin, the signal direction for that pin is determined by
the corresponding control bit in the port A data direction register (PADDR). The port I/O pin
is configured as an input if the corresponding PADDR bit is cleared; it is configured as an
output if the corresponding PADDR bit is set. All PACNT bits and PADDR bits are cleared
on total system reset, configuring all port A pins as general-purpose input pins. (Note that
these port pins do not have internal pullup resistors).
If a port A pin is selected as a general-purpose I/O pin, it may be accessed through the port
A data register (PADAT). Data written to the PADAT is stored in an output latch. If a port A
pin is configured as an output, the output latch data is gated onto the port pin. In this case,
when the PADAT is read, the contents of the output latch associated with the output port pin
are read. If a port A pin is configured as an input, data written to PADAT is still stored in the
output latch but is prevented from reaching the port pin. In this case, when PADAT is read,
the state of the port pin is read.
If a port A pin is selected as a dedicated on-chip peripheral pin, the corresponding bit in the
PADDR is ignored, and the direction of the pin is determined by the operating mode of the
on-chip peripheral. In this case, the PADAT contains the current state of the peripheral's in-
put pin or output driver.
Certain pins may be selected as general-purpose I/O pins, even when other pins related to
the same on-chip peripheral are used as dedicated pins. For example, a system that config-
ures SCC2 to operate in a nonmultiplexed mode without the modem control lines and exter-
nal clocks (RCLK2, TCLK2, CD2, CTS2, and RTS2) may dedicate the data lines (RXD2 and
TXD2) to SCC2 and configure the others as general-purpose I/O pins. What the peripheral
3-30
SCC2
TO
PADAT
BIT 0
TO
RXD2
OUTPUT
LATCH
BUFFER
INPUT
Figure 3-5. Parallel I/O Block Diagram for PA0
MUX
EN
0
1
16 BITS
PADDR
MC68302 USER’S MANUAL
0
1
MUX
EN
16 BITS
PACNT
1
0
MUX
EN
RXD2/PA0
MOTOROLA
PIN
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