MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 405
MC68302EH20C
Manufacturer Part Number
MC68302EH20C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH20C.pdf
(481 pages)
Specifications of MC68302EH20C
Processor Type
M683xx 32-Bit
Speed
20MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
20MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH20C PDF datasheet #4
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Since the L bit is set, once the frame ends, the synchronization process must occur once
again. Also, to force resynchronizations instead of waiting for the transmission to finish, a
STOP TRANSMIT command can be given, followed by a RESTART TRANSMIT command;
however, the STOP TRANSMIT command will abort the current buffer.
Figure D-27 shows how CD (sync) is used in the NMSI receive case. Setting the EXSYN bit
causes CD (sync) to control the reception of data. CD (sync) should be latched low on the
rising clock (RCLK) of the second bit of the frame. (Latching CD (sync) during the 2nd bit of
the frame allows external BISYNC sync detection logic, which also uses EXSYN, extra time
to present the external sync to the SCC.) Once synchronization is achieved, it will never be
lost unless an ENTER HUNT MODE command is given, a receive overrun occurs, or the
receiver is disabled and re-enabled (ENR bit is cleared, ENTER HUNT MODE command is
issued, and ENR is set). Once synchronization is lost, a new frame can be resynchronized
using CD (sync).
Notice that we have been discussing the receive and transmit cases separately. The receive
and transmit halves of the SCC really are separate and distinct; however, in transparent
mode, the receive and transmit halves of the SCC share the CD (sync) pin, which is not true
in normal NMSI.
MOTOROLA
CD (SYNC)
(OUTPUT)
(OUTPUT)
(INPUT)
(INPUT)
RCLK
TCLK
TXD
RTS
CTS
(I/O)
(I/O)
EXSYN = 1
NTSYN = 1
DIAG1-DIAG0 BITS = 11
L = 1 IN THE Tx BD
ONLY ONE Tx BD IS READY
DON'T
CARE
Figure D-26. Using CD (Sync) In the NMSI Transmit Case
DATA READY; WAITING FOR CD
CD BEING LATCHED HERE ON
RISING RCLK CAUSES DATA TO
BEGIN TRANSMITTING IN 6.5
BIT TIMES.
6.5 TCLKS
MC68302 USER’S MANUAL
FIRST BIT TRANSMITTED
NO EFFECT; ONLY THE FALLING
EDGE IS DETECTED.
LAST BIT
MC68302 Applications
D-55
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