MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 322

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
6.21 AC ELECTRICAL SPECIFICATIONS—PCM TIMING
There are two sync types:
6-34
NOTES:
Num.
301A
1. The ratio CLK/L1CLK must be greater than 2.5/1.
2. L1TxD becomes valid after the L1CLK rising edge or the sync enable, whichever is later, if long frames are used.
This note should only be used if the user can guarantee that only one sync pin (L1SY0 and L1SY1) is changed
simultaneously in the selection and de-selection of the desired PCM channel time slot. A safe example of this is
using only PCM CH-1. Another example is using CH-1 and CH-2 only, where CH-1 and CH-2 are not contiguous on
the PCM highway.
3. Specification valid for both sync methods.
4. Where P = 1/CLKO. Thus, for a 16.67-MHz CLKO rate, P = 60 ns.
300
301
302
303
304
305
306
307
308
309
Short Frame—Sync signals are one clock cycle prior to the data
Long Frame—Sync signals are N-bits that envelope the data
and Figure 6-23).
L1CLK (PCM Clock) Frequency (see Note
1)
L1CLK Width Low
L1CLK Width High (see Note 4)
L1SY0–L1SY1 Setup Time to L1CLK
Rising Edge
L1SY0–L1SY1 Hold Time from L1CLK
Falling Edge
L1SY0–L1SY1 Width Low
Time Between Successive Sync Signals
(Short Frame)
L1TxD Data Valid after L1CLK Rising Edge
(see Note 2)
L1TxD to High Impedance (from L1CLK
Rising Edge)
L1RxD Setup Time (to L1CLK Falling
Edge) (see Note 3)
L1RxD Hold Time (from L1CLK Falling
Edge) (see Note 3)
Characteristic
MC68302 USER’S MANUAL
P+10
Min
16.67 MHz
55
40
20
50
—
0
1
8
0
0
Max
6.66
—
—
—
—
—
—
70
50
—
—
P+10
Min
45
33
17
42
—
0
1
8
0
0
20 MHz
Max
8.0
60
42
—
—
—
—
—
—
—
—
P+10
,
Min
—
37
27
14
34
N > 0; see Figure 6-22
0
1
8
0
0
25 MHz
Max
10.0
47
34
—
—
—
—
—
—
—
—
MOTOROLA
L1CLK
L1CLK
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns