MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 134

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Communications Processor (CP)
The IDL interface supports the CCITT I.460 recommendation for data rate adaptation. The
IDL interface can access each bit of the B channel as an 8-kbps channel. A serial interface
mask register (SIMASK) for the B channels specifies which bits are supported by the IDL
interface. The receiver will support only the bits enabled by SIMASK. The transmitter will
transmit only the bits enabled by the mask register and will three-state L1TXD otherwise.
Refer to Figure 4-6 for an example of supporting two bits in the B1 channel and three bits in
the B2 channel.
4.4.2 GCI Interface
The normal mode of the GCI (also known as ISDN-Oriented Modular rev 2.2 (IOM2)) ISDN
bus is fully supported by the IMP. The IMP also supports channel 0 of the Special Circuit
Interface T (SCIT) interface, and in channel 2 of SCIT, supports the D channel access con-
trol for S/T interface terminals, using the command/indication (C/I) field. The IMP does not
support the Telecom IC (TIC) bus.
The GCI bus consists of four lines: two data lines, a clock, and a frame synchronization line.
Usually an 8-kHz frame structure defines the various channels within the 256-kbps data rate
as indicated in Figure 4-8. However, the interface can also be used in a multiplexed frame
structure on which up to eight physical layer devices multiplex their GCI channels. L1SY1
must provide the channel SYNC. In this mode, the data rate would be 2048 kbps.
The GCI clock rate is twice the data rate. The clock rate for the IMP must not exceed the
ratio of 1:2.5 serial clock to parallel clock. Thus, for a 16.67-MHz system clock, the serial
clock rate must not exceed 6.67 MHz.
The IMP also supports another line for D-channel access control—the L1GR line. This signal
is not part of the GCI interface definition and may be used in proprietary interfaces.
4-14
When the L1GR line is not used, it should be pulled high. The
IMP has two data strobe lines (SDS1 and SDS2) for selecting ei-
ther or both of the B1 and B2 channels and the data rate clock
(L1CLK). These signals are used for interfacing devices that do
not support the GCI bus. They are configured with the SIMASK
register and are active only for bits that are not masked.
MC68302 USER’S MANUAL
NOTE
MOTOROLA