MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 105
MC68302EH20C
Manufacturer Part Number
MC68302EH20C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH20C.pdf
(481 pages)
Specifications of MC68302EH20C
Processor Type
M683xx 32-Bit
Speed
20MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
20MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
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DISCPU should remain continuously high during disable CPU mode operation. Although the
CS0 pin is not available as an output from the device in disable CPU mode, it may be en-
abled to provide DTACK generation. In disable CPU mode, BR0 is initially $C000.
Accesses by an external master to the MC68302 RAM and registers may be asynchronous
or synchronous to the MC68302 clock. (This feature is actually available regardless of dis-
able CPU mode). See the SAM and EMWS bits in the SCR for details.
In disable CPU mode, the interrupt controller may be programmed to generate or not gen-
erate interrupt vectors during interrupt acknowledge cycles. When multiple MC68302 devic-
es share a single M68000 bus, vector generation at level 4 should be prevented on all but
one MC68302. When using disable CPU mode to implement an interface, such as between
the MC68020 and a single MC68302, vector generation can be enabled. For this purpose,
the VGE bit is defined.
VGE—Vector Generation Enable
In disable CPU mode, the low-power modes will be entered immediately upon the setting of
the LPEN bit in the SCR by an external master. In this case, low-power mode will continue
until the LPEN bit is cleared. Users may wish to use a low-power mode in conjunction with
disable CPU mode to save power consumed by the disabled M68000 core.
All MC68302 functionality not expressly mentioned in this section is retained in disable CPU
mode and operates identically as before.
MOTOROLA
2. BG will be an input to the IDMA and SDMA from the external M68000 bus, rather than
3. BCLR will be an input to the IDMA, but will remain an output from the SDMA.
4. The interrupt controller will output its interrupt request lines (IPL0, IPL1, IPL2) normally
0 = In disable CPU mode, the MC68302 will not output interrupt vectors during inter-
1 = In disable CPU mode, the MC68302 will output interrupt vectors for internal level 4
being an output from the MC68302. When BG is sampled as low by the MC68302, it
waits for AS, BERR, HALT, and BGACK to be negated, and then asserts BGACK and
performs one or more bus cycles. See Section 6 for timing diagrams.
sent to the M68000 core on pins IOUT0, IOUT1, and IOUT2, respectively. AVEC,
RMC, and CS0, which share pins with IOUT0, IOUT1, and IOUT2, respectively, are
not available in this mode.
rupt acknowledge cycles.
interrupts (and for levels 1, 6, and/or 7 as enabled in the interrupt controller) during
interrupt acknowledge cycles.
Do not use the function code value “111” during external access-
es to the IMP, except during interrupt acknowledge cycles.
Even without the use of the disable CPU logic, another proces-
sor can be granted access to the IMP on-chip peripherals by re-
MC68302 USER’S MANUAL
NOTE
NOTE
System Integration Block (SIB)
3-55
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