MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 25

IC MPU MULTI-PROTOCOL 132-PQFP

MC68302EH20C

Manufacturer Part Number
MC68302EH20C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor

Specifications of MC68302EH20C

Processor Type
M683xx 32-Bit
Speed
20MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
20MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC68302EH20C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MC68302EH20C
Manufacturer:
XILINX
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Part Number:
MC68302EH20CB1
Manufacturer:
Freescale Semiconductor
Quantity:
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Part Number:
MC68302EH20CR2
Manufacturer:
Freescale Semiconductor
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The MC68302 can also be used in applications such as board-level industrial controllers
performing real-time control applications with a local control bus and an X.25 packet network
connection. Such a system provides the real-time response to a demanding peripheral while
permitting remote monitoring and communication through an X.25 packet network.
1.2 FEATURES
The features of the IMP are as follows:
3.
MOTOROLA
IOM is a trademark of Siemens AG
• On-Chip HCMOS MC68000/MC68008 Core Supporting a 16- or 8-Bit M68000 Family-
• IB Including:
• CP Including:
System
—Independent Direct Memory Access (IDMA) Controller with Three Handshake
—Interrupt Controller with Two Modes of Operation
—Parallel Input/Output (I/O) Ports, Some with Interrupt Capability
—On-Chip 1152-Byte Dual-Port RAM
—Three Timers Including a Watchdog Timer
—Four Programmable Chip-Select Lines with Wait-State Generator Logic
—Programmable Address Mapping of the Dual-Port RAM and IMP Registers
—On-Chip Clock Generator with Output Signal
—System Control:
—Main Controller (RISC Processor)
—Three Independent Full-Duplex Serial Communications Controllers (SCCs)
—Supporting Various Protocols:
—Six Serial DMA Channels for the Three SCCs
—Flexible Physical Interface Accessible by SCCs Including:
Signals:
Bus Arbitration Logic with Low-Interrupt Latency Support
System Status and Control Logic
Disable CPU Logic (M68000)
Hardware Watchdog
Low-Power (Standby) Modes
Freeze Control for Debugging
DRAM Refresh Controller
High-Level/Synchronous Data Link Control (HDLC/SDLC)
Universal Asynchronous Receiver Transmitter (UART)
Binary Synchronous Communication (BISYNC)
Synchronous/Asynchronous Digital Data Communications Message
Protocol (DDCMP)
Transparent Modes
V.110 Rate Adaption
Motorola Interchip Digital Link (IDL)
General Circuit Interface (GCI, also known as IOM
Pulse Code Modulation (PCM) Highway Interface
DREQ
,
DACK
, and
MC68302 USER’S MANUAL
DONE
.
3
-2)
General Description
1-3

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