MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 187

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The 8- or 16-bit control field provides a flow control number and defines the frame type (con-
trol or data). The exact use and structure of this field depends upon the protocol using the
frame.
Data is transmitted in the data field, which can vary in length depending upon the protocol
using the frame. Layer 3 frames are carried in the data field.
Error control is implemented by appending a cyclic redundancy check (CRC) to the frame,
which is 16-bits long in most protocols, but may be 32-bits long in some.
When the MODE1–MODE0 bits of an SCC mode register (SCM) select the HDLC mode,
then that SCC functions as an HDLC controller. The HDLC controller handles the basic func-
tions of the HDLC/SDLC protocol on either the D channel, a B channel, or from a multiplexed
serial interface (IDL, GCI (IOM-2), or PCM highway). When the HDLC controller is used to
support the B or D channel of the ISDN, the SCC outputs are internally connected to the
physical layer serial interface.
When an SCC in HDLC mode is used with a nonmultiplexed modem interface, then the SCC
outputs are connected directly to the external pins. In this case, the serial interface uses sev-
en dedicated pins: transmit data (TXD), receive data (RXD), receive clock (RCLK), transmit
clock (TCLK), carrier detect (CD), clear to send (CTS), and request to send (RTS). Other
modem signals may be supported through the parallel I/O pins.
The HDLC controller consists of separate transmit and receive sections whose operations
are asynchronous with the M68000 core and may be either synchronous or asynchronous
with respect to the other SCCs. Up to eight frames may be transmitted or received without
M68000 core intervention. When the HDLC controller is connected to one of the multiplexed
physical interface options (IDL, GCI, or PCM highway), the receive and transmit clocks are
identical and are supplied externally by the physical layer. In non-ISDN applications, each
clock can be supplied either from the baud rate generator or externally. The baud rate gen-
erator is discussed more fully in 4.5.2 SCC Configuration Register (SCON).
The HDLC controller key features are as follows:
MOTOROLA
• Flexible Data Buffers with Multiple Buffers per Frame Allowed
• Separate Interrupts for Frames and Buffers (Receive and Transmit)
• Four Address Comparison Registers with Mask
• Maintenance of Five 16-Bit Error Counters
• Flag/Abort/Idle Generation/Detection
• Zero Insertion/Deletion
• NRZ/NRZI Data Encoding
• 16-Bit or 32-Bit CRC-CCITT Generation/Checking
SDLC is fully supported, but the SDLC loop mode (ring configu-
ration) is not supported.
MC68302 USER’S MANUAL
NOTE
Communications Processor (CP)
4-67