MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 193

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Error Counters
4.5.12.9 HDLC Mode Register
Each SCC mode register is a 16-bit, memory-mapped, read-write register that controls the
SCC operation. The term HDLC mode register refers to the protocol-specific bits (15–6) of
MOTOROLA
MSB
3. Abort Sequence. An abort sequence is detected by the HDLC controller when seven
4. Nonoctet Aligned Frame. When this error occurs, the channel writes the received data
5. CRC Error. When this error occurs, the channel writes the received CRC to the data
The CP maintains five 16-bit (modulo - 2**16) error counters for each HDLC controller.
They can be initialized by the user when the channel is disabled. The counters are as fol-
lows:
is not programmed to control this line with software, the channel terminates frame re-
ception, closes the buffer, sets the carrier detect lost (CD) bit in the BD, and generates
the RXF interrupt (if enabled). This error has the highest priority. The rest of the frame
is lost, and other errors are not checked in that frame. The receiver then enters the
hunt mode.
or more consecutive ones are received while receiving a frame. When this error oc-
curs, the channel closes the buffer by setting the Rx abort sequence (AB) bit in the BD
and generates the RXF interrupt (if enabled). The channel also increments the abort
sequence counter (ABTSC). The receiver then enters hunt mode immediately. The
CRC and nonoctet error status conditions are not checked on aborted frames. The re-
ceiver then enters hunt mode.
to the data buffer, closes the buffer, sets the Rx nonoctet aligned frame (NO) bit in the
BD, and generates the RXF interrupt (if enabled). The CRC error status should be dis-
regarded on nonoctet frames. After a nonoctet aligned frame is received, the receiver
enters hunt mode. (An immediately following back-to-back frame will be received.) The
nonoctet data may be derived from the last word in the data buffer as follows:
Consistent with other HDLC operation, the MSB is the first bit received in this word,
and the low-order valid data bit is the last.
buffer, closes the buffer, sets the CR bit in the BD, and generates the RXF interrupt (if
enabled). The channel also increments the CRC error counter (CRCEC). After receiv-
ing a frame with a CRC error, the received enters hunt mode. (An immediately follow-
ing back-to-back frame will be received.) CRC checking cannot be disabled, but the
CRC error may be ignored if checking is not required.
DISFC—Discarded Frame Counter (error-free frames but no free buffers)
CRCEC—CRC Error Counter (includes frames not addressed to the user or frames
received in the BSY condition, but does not include overrun errors)
ABTSC—Abort Sequence Counter
NMARC—Nonmatching Address Received Counter (error-free frames only)
RETRC—Frame Retransmission Counter (due to collision)
VALID DATA
MC68302 USER’S MANUAL
1
0
Communications Processor (CP)
NOT VALID DATA
LEADING ZEROS
• • •
LSB
4-73
0