MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 44

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MC68000/MC68008 Core
CFC—Compare Function Code
Bits 11–0—Base Address
2.8 MC68302 MEMORY MAP
The following tables show the additional registers added to the M68000 to make up the
MC68302. All of the registers are memory-mapped. Four entries in the M68000 exception
vectors table (located in low RAM) are reserved for addresses of system configuration reg-
isters (see Table 2-6) that reside on-chip. These registers have fixed addresses of $0F0–
$0FF. All other on-chip peripherals occupy a 4K-byte relocatable address space. When an
on-chip register or peripheral is accessed, the internal access (IAC) pin is asserted.
The internal 1176-byte dual-port RAM has 576 bytes of system RAM (see Table 2-7) and
576 bytes of parameter RAM (see Table 2-8).
The parameter RAM contains the buffer descriptors for each of the three SCC channels, the
SCP, and the two SMC channels. The memory structures of the three SCC channels are
2-14
The high address field is contained in bit 11–0 of the BAR. These bits are used to set the
starting address of the dual-port RAM. The address compare logic uses only the most sig-
nificant bits to cause an address match within its block size.
0 = The FC bits in the BAR are ignored. Accesses to the IMP 4K-byte block occur with-
1 = The FC bits in the BAR are compared. The address space compare logic uses the
out comparing the FC bits.
FC bits to detect address matches.
*
Reset only upon a total system reset.
Address
Base + 23F
Base + 3FF
Base + 000
$0F2
$0F4
$0FC
Base +240
$0F0
$0FA
$0F8
Address
•
•
•
•
•
•
*
*
Table 2-6. System Configuration Register
Name
CKCR
RES
BAR
SCR
RES
RES
576 Bytes
Width
Table 2-7. System RAM
MC68302 USER’S MANUAL
Width
16
16
32
16
16
32
Reserved
Base Address Register
System Control Register
Reserved
Clock Control Register
Reserved
Block
RAM
Description
User Data Memory
(Not Implemented)
Description
Reserved
Reset Value
0000 0F00
BFFF
0000
MOTOROLA