MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 71

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

3.2.4 Interrupt Vector
Pending EXRQ interrupts and unmasked INRQ interrupts are presented to the M68000 core
in order of priority. The M68000 core responds to an interrupt request by initiating an inter-
rupt acknowledge cycle to receive a vector number, which allows the core to locate the in-
terrupt's service routine.
If an INRQ source generated the interrupt, the interrupt controller always provides the vector
corresponding to the highest priority, unmasked, pending interrupt. If an EXRQ source gen-
erated the interrupt, three options are available to generate the vector.
Option 1. By programming the GIMR, the user can enable the interrupt controller to provide
the vector for any combination of EXRQ interrupt levels 1, 6, and 7. This is available regard-
less of whether normal or dedicated mode is selected. Whenever a vector is provided by the
interrupt controller, DTACK is also provided by the interrupt controller during that interrupt
acknowledge cycle. DTACK is an output from the IMP in this case.
The IMP can generate vectors for up to seven external peripherals by connecting the exter-
nal request lines to IRQ7, IRQ6, IRQ1, PB11, PB10, PB9, and PB8. PB11, PB10, PB9, and
PB8 are prioritized within level 4.
MOTOROLA
EVENT
MASK
Figure 3-3. Interrupt Request Logic Diagram for SCCs
BIT
BIT
SCCM
SCCE
8-INPUT
MC68302 USER’S MANUAL
OR
IPR
IMR
16-INPUT
OR
INTERRUPT
RESOLVER
PRIORITY
INTERNAL IPL2–IPL0
TO THE M68000 CORE
System Integration Block (SIB)
3-21