MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 122

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Communications Processor (CP)
buffer descriptors of the serial channels. Also, a number of protocol-specific parameters are
exchanged through several parameter RAM areas in the internal dual-port RAM.
The RISC controller uses the peripheral bus to communicate with all its peripherals. Each
SCC has a separate transmit and receive FIFO. Depending on the protocol chosen, the
transmit FIFO is either 3 bytes or 4 words, and the receive FIFO is either 3 bytes or 3 words.
Each SCC is configured by parameters written to the dual-port RAM and by SCC hardware
registers that are written by the M68000 core (or an external master). The SCC registers that
configure each SCC are the SCON, DSR, and SCM. There are three sets of these registers,
one for each SCC. The serial channels physical interface is configured by the M68000 core
through the SIMODE and SIMASK registers.
Simultaneous access of the dual-port RAM by the main controller and the M68000 core (or
external processor) is prevented. During a standard four-clock cycle access of the dual-port
RAM by the M68000 core, three main controller accesses are permitted. The main controller
is delayed one clock cycle, at most, in accessing the dual-port RAM.
The main controller has a priority scheduler that determines which microcode routine is
called when more than one internal request is pending. Requests are serviced in the follow-
ing priority:
4-2
1. CP or System Reset
2. SDMA Bus Error
PB8 REQUEST
CONTROLLER
RISC
CR REQUEST
SERIAL SERVICE
REQUESTS
CR
CHANNELS
SERIAL
OTHER
Figure 4-1. Simplified CP Architecture
CHANNELS
6 SDMA
FIFO
MC68302 USER’S MANUAL
SCC1
PERIPHERAL BUS
FIFO
SERIAL CHANNELS PHYSICAL INTERFACE
M68000 DATA BUS
MICROCODE
FIFO
ROM
SCC2
FIFO
FIFO
SYSTEM
RAM
SCC3
DUAL-PORT RAM
FIFO
PARAMETER
RAM
REGISTERS
REGISTERS
PHYSICAL
SCC
H/W
I/F
MOTOROLA