MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 218

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Communications Processor (CP)
nized by the BISYNC channel and to generate interrupts. On recognition of an event, the
BISYNC controller sets the corresponding bit in the BISYNC event register. Interrupts gen-
erated by this register may be masked in the BISYNC mask register.
The BISYNC event register is a memory-mapped register that may be read at any time. A
bit is cleared by writing a one (writing a zero does not affect a bit's value). More than one bit
may be cleared at a time. All unmasked bits must be cleared before the CP will negate the
internal interrupt request signal. This register is cleared at reset.
CTS—Clear-To-Send Status Changed
CD—Carrier Detect Status Changed
Bit 5—Reserved for future use.
TXE—Tx Error
RCH—Receive Character
BSY—Busy Condition
TX—Tx Buffer
RX—Rx Buffer
A complete buffer has been received on the BISYNC channel.
4.5.13.13 BISYNC Mask Register
The SCC mask register (SCCM) is referred to as the BISYNC mask register when the SCC
is operating as a BISYNC controller. It is an 8-bit read-write register that has the same bit
format as the BISYNC event register. If a bit in the BISYNC mask register is a one, the cor-
responding interrupt in the event register will be enabled. If the bit is zero, the corresponding
interrupt in the event register will be masked. This register is cleared upon reset.
4-98
A change in the status of the serial line was detected on the BISYNC channel. The SCC
status register may be read to determine the current status.
A change in the status of the serial line was detected on the BISYNC channel. The SCC
status register may be read to determine the current status.
An error (CTS lost or underrun) occurred on the transmitter channel.
A character has been received and written to the buffer.
A character was received and discarded due to lack of buffers. The receiver will resume
reception after an ENTER HUNT MODE command.
A buffer has been transmitted. This bit is set on the second to last bit of BCC or data.
CTS
7
CD
6
MC68302 USER’S MANUAL
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5
TXE
4
RCH
3
BSY
2
TX
1
RX
0
MOTOROLA