MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 192

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Communications Processor (CP)
and the frame length in the last BD. MFLR is defined as all the in-frame bytes between the
opening flag and the closing flag (address, control, data, and CRC). MAX_CNT is a tempo-
rary downcounter used to track the frame length.
4.5.12.8 HDLC Error-Handling Procedure
The HDLC controller reports frame reception and transmission error conditions using the
channel BDs, the error counters, and the HDLC event register. The modem interface lines
can also be directly monitored in the SCC status register.
Transmission Errors:
Reception Errors:
4-72
1. Transmitter Underrun. When this error occurs, the channel terminates buffer transmis-
2. Clear-To-Send Lost (Collision) During Frame Transmission. When this error occurs
1. Overrun Error. The HDLC controller maintains an internal three-word FIFO for receiv-
2. Carrier Detect Lost During Frame Reception. When this error occurs and the channel
sion, closes the buffer, sets the underrun (UN) bit in the BD, and generates the TXE
interrupt (if enabled). The channel will resume transmission after the reception of the
RESTART TRANSMIT command. The transmit FIFO size is four words.
and the channel is not programmed to control this line with software, the channel ter-
minates buffer transmission, closes the buffer, sets the CTS lost (CT) bit in the BD,
and generates the TXE interrupt (if enabled). The channel will resume transmission af-
ter the RESTART TRANSMIT command is given.
ing data. The CP begins programming the SDMA channel (if the data buffer is in ex-
ternal memory) and updating the CRC when the first word is received in the FIFO.
When a receive FIFO overrun occurs, the channel writes the received data byte to the
internal FIFO over the previously received byte. The previous data byte and the frame
status are lost. Then the channel closes the buffer with the overrun (OV) bit in the BD
set and generates the RXF interrupt (if enabled). The receiver then enters the hunt
mode.
Even if the overrun occurs during a frame whose address is not matched in the ad-
dress recognition logic, a BD of length two will be opened to report the overrun, and
the RXB interrupt will be generated (if enabled).
If this error occurs on the first or second buffer of the frame and
the retransmit enable (RTE) bit in the HDLC mode register is set,
the channel will retransmit the frame when the CTS line be-
comes active again. When using this feature, users should de-
sign transmit frames to fit within two buffers or less. When
working in ISDN mode with D-channel collision possibility, to en-
sure the retransmission method functions properly, the first and
second data buffers should contain more than 10 bytes of data
if multiple buffers per frame are used. (Small frames consisting
of a single buffer are not subject to this requirement). The chan-
nel will also increment the retransmission counter (RETRC).
MC68302 USER’S MANUAL
NOTE
MOTOROLA