MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 294

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
6.8 AC ELECTRICAL SPECIFICATIONS—IMP BUS MASTER CYCLES
6-6
Num.
14A
20A
11
12
13
14
15
16
17
18
20
21
22
23
25
26
27
28
29
30
31
32
33
34
35
36
6
7
8
9
(see Figure 6-2, Figure 6-3, Figure 6-4, and Figure 6-5))
Clock High to FC, Address Valid
Clock High to Address, Data Bus High Im-
pedance (Maximum)
Clock High to Address, FC Invalid (Mini-
mum)
Clock High to AS, DS Asserted (see Note 1)
Address, FC Valid to AS, DS Asserted
(Read) AS Asserted Write (see Note 2)
Clock Low to AS, DS Negated (see Note 1)
AS, DS Negated to Address, FC Invalid (see
Note 2)
AS (and DS Read) Width Asserted (see
Note 2)
DS Width Asserted, Write (see Note 2)
AS, DS Width Negated (see Note 2)
Clock High to Control Bus High Impedance
AS, DS Negated to R/W Invalid (see Note 2)
Clock High to R/W High (see Note 1)
Clock High to R/W Low (see Note 1)
AS Asserted to R/W Low (Write) (see Notes
2 and 6)
Address FC Valid to R/W Low (Write) (see
Note 2)
R/W Low to DS Asserted (Write) (see Note
2)
Clock Low to Data-Out Valid
AS, DS, Negated to Data-Out Invalid (Write)
(see Note 2)
Data-Out Valid to DS Asserted (Write) (see
Note 2)
Data-In Valid to Clock Low (Setup Time on
Read) (see Note 5)
AS, DS Negated to DTACK Negated (Asyn-
chronous Hold) (see Note 2)
AS, DS Negated to Data-In Invalid (Hold
Time on Read)
AS, DS Negated to BERR Negated
DTACK Asserted to Data-In Valid (Setup
Time) (see Notes 2 and 5)
HALT and RESET Input Transition Time
Clock High to BG Asserted
Clock High to BG Negated
BR Asserted to BG Asserted (see Note 11)
BR Negated to BG Negated (see Note 7)
Characteristic
MC68302 USER’S MANUAL
t
t
Symbol
CHFCADV
t
t
RHr
t
t
t
t
AFCVRL
t
AFCVSL
t
t
t
t
t
t
BRHGH
CHADZ
t
t
t
t
t
t
SHDAH
SHBEH
t
t
t
t
BRLGL
t
SHDOI
CHAFI
SHAFI
CHRH
t
DALDI
CHGH
CHCZ
SHRH
CHRL
ASRV
CLDO
DOSL
CHGL
CHSL
CLSH
t
SHDII
RLSL
DICL
t
t
DSL
SH
SL
, t
RHf
Min
16.67 MHz
120
2.5
1.5
15
15
60
60
15
15
30
15
15
—
—
—
—
—
—
—
—
—
—
—
0
0
3
7
0
0
0
Max
110
150
4.5
2.5
45
50
30
30
50
30
30
10
30
50
30
30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min
100
2.5
1.5
12
12
50
50
12
12
25
12
12
—
—
—
—
—
—
—
—
—
—
—
0
0
3
6
0
0
0
20 MHz
Max
150
4.5
2.5
40
42
—
25
—
25
—
—
—
—
42
—
25
25
10
—
—
25
—
—
—
95
—
—
42
25
25
Min
2.5
1.5
10
10
80
40
40
10
10
20
10
10
—
—
—
—
—
—
—
—
—
—
—
0
0
3
5
0
0
0
25 MHz
Max
150
4.5
2.5
MOTOROLA
30
33
20
20
33
20
20
20
75
33
20
20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7
Unit
clks
clks
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns