MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 202

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Communications Processor (CP)
IDL—IDLE Sequence Status Changed
TXE—Tx Error
RXF—Rx Frame
BSY—Busy Condition
TXB—Tx Buffer
RXB—Rx Buffer
4.5.12.13 HDLC Mask Register
The SCC mask register (SCCM) is referred to as the HDLC mask register when the SCC is
operating as an HDLC controller. It is an 8-bit read-write register that has the same bit for-
mats as the HDLC event register. If a bit in the HDLC mask register is a one, the correspond-
ing interrupt in the event register will be enabled. If the bit is zero, the corresponding interrupt
in the event register will be masked. This register is cleared upon reset.
4.5.13 BISYNC Controller
The byte-oriented binary synchronous communication (BISYNC) protocol was originated by
IBM for use in networking products. The three classes of BISYNC frames are transparent,
non-transparent with header, and non-transparent without header (see Figure 4-30). The
transparent mode in BISYNC allows full binary data to be transmitted, with any possible
character pattern allowed. Each class of frame starts with a standard two octet synchroni-
zation pattern and ends with a block check code (BCC). The end of text character (ETX) is
used to separate the text and BCC fields.
4-82
A change in the status of the serial line was detected on the HDLC channel. The SCC sta-
tus register may be read to determine the current status.
An error (CTS lost or underrun) occurred on the transmitter channel.
A complete frame has been received on the HDLC channel. This bit is set no sooner than
two receive clocks after receipt of the last bit of the closing flag.
A frame was received and discarded due to lack of buffers.
A buffer has been transmitted on the HDLC channel. This bit is set no sooner than when
the second-to-last bit of the closing flag begins its transmission, if the buffer is the last in
the frame. Otherwise, it is set after the last byte of the buffer has been written to the trans-
mit FIFO.
A buffer has been received on the HDLC channel that was not a complete frame. This bit
will only be set if the I bit in the Tx BD was set.
MC68302 USER’S MANUAL
MOTOROLA