MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 154

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Communications Processor (CP)
table, after processing of this BD is complete. After using a BD, the CP sets the “ready” bit
to not-ready; thus, the CP will never use a BD twice until the BD has been confirmed by the
M68000 core.
The CP uses the receive BDs in a similar fashion. Once the receive side of an SCC is en-
abled, it starts with the first BD in that SCC's receive BD table. Once data arrives from the
serial line into the SCC, the CP performs certain required protocol processing on the data
and moves the resultant data (either bytes or words at a time depending on the protocol) to
the buffer pointed to by the first BD. Use of a BD is complete when there is no more room
left in the buffer or when certain events occur, such as detection of an error or an end-of-
frame. Whatever the reason, the buffer is then said to be “closed,” and additional data will
be stored using the next BD. Whenever the CP needs to begin using a BD because new
data is arriving, it will check the “empty” bit of that BD. If the current BD is not empty, it will
report a” busy” error. However, it will not move from the current BD until it becomes empty.
When the CP sees the “wrap” bit set in a BD, it goes back to the beginning of the BD table,
after use of this BD is complete. After using a BD, the CP sets the “empty” bit to not-empty;
thus, the CP will never use a BD twice until the BD has been “processed” by the M68000
core.
In general, each SCC has eight transmit BDs and eight receive BDs. However, it is possible
in one special case to assign up to 16 receive BDs at the expense of all transmit BDs. Since
the transmit BDs directly follow the receive BDs in the memory map for each SCC, if an SCC
is configured exclusively for half-duplex reception, it is possible to have up to 16 receive BDs
available for that SCC.
If the DRAM refresh unit is used, SCC2 has six transmit BDs rather than the normal eight.
SCC3 normally only has four transmit BDs. However, it is actually possible to regain addi-
tional Tx BDs for SCC3 as follows. The Tx BD table may be extended by two BDs to six BDs
if the SMCs are not used. Additionally, all eight Tx BDs for SCC3 may be used if the following
is considered: 1) the SCP and SMCs must not be used; 2) various words within the last two
BDs will be changed by the CP during the initialization routine following any reset; and 3)
the BERR channel number value will be written into the last BD after any SDMA bus error
(see 4.5.8.4 Bus Error on SDMA Access), but this is not a major concern since the CP must
be reset after any SDMA bus error.
4.5.6 SCC Parameter RAM Memory Map
Each SCC maintains a section in the dual-port RAM called the parameter RAM. Each SCC
parameter RAM area begins at offset $80 from each SCC base area ($400, $500, or $600)
and continues through offset $BF. Refer to Table 2-8 for the placement of the three SCC
parameter RAM areas. Part of each SCC parameter RAM (offset $80–$9A), which is iden-
tical for each protocol chosen, is shown in Table 4-6. Offsets $9C–$BF comprise the proto-
col-specific portion of the SCC parameter RAM and are discussed relative to the particular
protocol chosen.
4-34
MC68302 USER’S MANUAL
MOTOROLA