MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 148

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Communications Processor (CP)
If RTS is programmed to be asserted by the SCC, it will be asserted once buffered data is
loaded into the transmit FIFO and a falling TCLK edge occurs. The following table shows
the transmit data delays.
RTS is negated by the SCC one clock after the last bit in the frame. Figure 4-13 shows a
diagram of synchronous mode timing from RTS low. Figure 4-14 shows a diagram of syn-
chronous mode timing delays from CTS low.
The SCC samples CTS on the every rising edge of the TCLK. If CTS is negated when RTS
is asserted, a CTS lost error occurs. If a synchronous protocol is used, the transmit data will
be aborted after four additional bits are transmitted. If an asynchronous protocol is used, the
transmit data will be aborted after three additional bits are transmitted. See the transmit error
section of each protocol for further details and steps to be taken following a CTS lost error.
The SCC latches its first bit of valid receive data on the same clock edge (rising RCLK) that
samples CD as low. The only exception is when the EXSYN bit is set in the SCC mode reg-
ister for the BISYNC and Transparent protocols.
If CD is negated during frame reception, a CD lost error occurs and the SCC will quit receiv-
ing data within four additional bit times. At this point, any residue of bits less than 8 bits (or
16 bits in HDLC or transparent modes) will be discarded and not written to memory. Thus,
the last bit written to memory will be within plus or minus four bit times from the point at which
CD was negated.
4-28
01 =
In this mode, the transmitter output is internally connected to the receiver input
while the receiver and the transmitter operate normally. The value on the RXD pin
is ignored. For the NMSI2 and NMSI3 pins, the TXD pin may be programmed to
either show the transmitted data or not show the data by programming port A par-
Loopback mode
The CTS lost error and CD lost error (with CTS and CD under
automatic control) is not intended to implement a flow control
method in the UART protocol. The software operation of the
DIAG1–DIAG0 bits should be chosen if UART flow control is de-
sired, with transmission being temporarily suspended by the
FRZ bit in the UART event register. CTS lost and CD lost, as de-
fined here, are intended to implement the aborting of transmis-
sion and reception as defined in many synchronous protocols.
NOTES:
1.RTS low values assume CTS is already asserted when RTS is asserted.
2.CTS low values assume CTS met the asynchronous setup time;
Asynchronous Protocols (16x clock)
Synchronous Protocols (1x clock)
otherwise, an additional clock may be added.
Table 4-5. Transmit Data Delay (TCLK Periods)
Protocol Type
MC68302 USER’S MANUAL
NOTE
RTS Low
From
0
1
CTS Low
From
3.5
48
MOTOROLA