MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 203

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

NON TRANSPARENT WITH HEADER
NON TRANSPARENT WITHOUT HEADER
TRANSPARENT
The bulk of the frame is divided into fields whose meaning depends on the frame type. The
BCC is either a 16-bit CRC (CRC-16) format if 8-bit characters are used or a longitudinal
check (a sum check) in combination with vertical redundancy check (parity) if 7-bit charac-
ters are used. In transparent operation, to allow the BISYNC control characters to be present
in the frame as valid text data, a special character (DLE) is defined, which informs the re-
ceiver that the character following the DLE is a text character, not a control character (from
the control character table). If a DLE is transmitted as valid data, it must be preceded by a
DLE character. This procedure is sometimes called byte-stuffing.
The physical layer of the BISYNC communications link must provide a means of synchro-
nizing the receiver and transmitter, which is usually accomplished by sending at least one
pair of synchronization characters prior to every frame.
BISYNC has the unusual property that a transmit underrun need not be an error. If an un-
derrun occurs, the synchronization pattern is transmitted until data is once again ready to
transmit. The receiver discards the additional synchronization characters as they are re-
ceived, provided the V bit is set in the BISYNC-BISYNC SYNC register. In non-transparent
operation, all synchronization characters (SYNCs) are discarded if the V bit is set in the BI-
SYNC-BISYNC SYNC register. In transparent operation, all DLE-SYNC pairs are discarded.
(Note that correct operation in this case assumes that, on the transmit side, the underrun
does not occur between the DLE and its following character, a failure mode prevented in the
MC68302.)
By appropriately setting the SCC mode register, any of the SCC channels may be config-
ured to function as a BISYNC controller. The BISYNC controller handles the basic functions
of the BISYNC protocol in normal mode and in transparent mode.
The SCC in BISYNC mode can work with IDL, GCI (IOM2), PCM highway, or NMSI interfac-
es. When the SCC in BISYNC mode is used with a modem interface (NMSI), the SCC out-
puts are connected directly to the external pins. The modem interface uses seven dedicated
pins: transmit data (TXD), receive data (RXD) receive clock (RCLK), transmit clock (TCLK),
carrier detect (CD), clear to send (CTS), and request to send (RTS). Other modem lines can
be supported using the parallel I/O pins.
The BISYNC controller consists of separate transmit and receive sections whose operations
are asynchronous with the M68000 core and may be either synchronous or asynchronous
with respect to the other SCCs. Each clock can be supplied from either the internal baud
MOTOROLA
SYN1
SYN1
SYN1
SYN2
SYN2
SYN2
Figure 4-30. Typical BISYNC Frames
SOH
DLE
STX
MC68302 USER’S MANUAL
STX
HEADER
TRANSPARENT
TEXT
TEXT
STX
TEXT
Communications Processor (CP)
DLE
ETX
ETX
ETX
BCC
BCC
BCC
4-83