MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 248

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Communications Processor (CP)
Once synchronization is achieved for the transmitter, it will remain in effect until an error oc-
curs, a STOP TRANSMIT command is given, or a buffer has completed transmission with
the Tx BD last (L) bit set. Once synchronization is achieved for the receiver, it will remain in
effect until an error occurs or the ENTER HUNT MODE command is given.
4.5.16.6 Transparent Error-Handling Procedure
The transparent controller reports message reception and transmission error conditions us-
ing the channel BDs and the transparent event register. The modem interface lines can also
be directly monitored in the SCC status register.
Transmission Errors:
Reception Errors:
4-128
5. With the physical interface configured for IDL or GCI mode, the SCC may be config-
1. Transmitter Underrun—When this error occurs, the channel terminates buffer trans-
2. Clear-To-Send Lost During Message Transmission—When this error occurs and the
1. Overrun Error—The transparent controller maintains an internal three-word FIFO for
ured with the EXSYN bit set and the DIAG1–DIAG0 bits set to either software opera-
tion or normal operation. In this case, the data will be byte-aligned to the B or D
channel time slots.
mission, closes the buffer, sets the underrun (UN) bit in the BD, and generates the
TXE interrupt (if enabled). The channel resumes transmission after the reception of
the RESTART TRANSMIT command. Underrun can occur after a transmit frame for
which the L bit in the Tx BD was not set. In this case, only the TXE bit is set. The FIFO
size is four words in transparent mode.
channel is not programmed to control this line with software, the channel terminates
buffer transmission, closes the buffer, sets the CTS lost (CT) bit in the BD, and gener-
ates the TXE interrupt (if enabled). The channel will resume transmission after the re-
ception of the RESTART TRANSMIT command.
receiving data. The CP begins programming the SDMA channel (if the data buffer is
in external memory) when the first word is received into the FIFO. If a FIFO overrun
occurs, the transparent controller writes the received data word to the internal FIFO
over the previously received word. The previous word is lost. Next, the channel closes
This technique is not valid for the PCM envelope sync method
when the time slots are less than six bits in length. In such a
case, the user may clear EXSYN to cause transmission to begin,
and then, for the receiver, provide the required SYN1–SYN2 se-
quence. To accomplish this, the user may configure the SCC to
loopback mode with the EXSYN bit cleared and the DSR set to
$FFFF. Then after 16 serial clocks, the receiver and transmitter
are synchronized, and the SCC may be dynamically reconfig-
ured to normal or software operation. At this point, reception be-
gins immediately, and transmission begins after the transmit BD
is made ready.
MC68302 USER’S MANUAL
NOTE
MOTOROLA