MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 295

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
NOTES:
1. For loading capacitance of less than or equal to 50 pF, subtract 4 ns from the value given in the maximum
2. Actual value depends on clock period since signals are driven/latched on different CLKO edges. To calculate
3. If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is a
Num.
37A
57A
58A
37
38
39
40
41
44
46
47
48
53
55
56
57
58
60
61
62
63
64
columns.
the actual spec for other clock frequencies, the user may derive the formula for each specification. First, derive
the margin factor as: M = N(P/2) - Sa
is the rated clock period of the device for which the specs were derived (e.g., 60 ns with a 16.67-MHz device or
50 ns with a 20 MHz device), and Sa is the actual spec in the data sheet. Thus, for spec 14 at 16.67 MHz:
with period (Pa) is calculated as:
These two formulas assume a 50% duty cycle. Otherwise, if N is odd, the previous values N(P/2) and N(Pa/2)
must be reduced by X, where X is the difference between the nominal pulse width and the minimum pulse width
of the EXTAL input clock for that duty cycle.
where N is the number of one-half CLKO periods between the two events as derived from the timing diagram, P
Once the margin (M) is calculated for a given spec, a new value of that spec (Sn) at another clock frequency
Thus for spec 14 at 12.5 MHz:
Sn = 5(80 ns/2) - 30 ns = 170 ns.
M = 5(60 ns/2) - 120 ns = 30 ns.
Sn = N(Pa/2) - M
BGACK Asserted to BG Negated
BGACK Asserted to BR Negated (see Note
8)
BG Asserted to Control, Address, Data Bus
High Impedance (AS Negated)
BG Width Negated
BGACK Asserted to Address Valid
BGACK Asserted to AS Asserted
AS, DS Negated to AVEC Negated
BGACK Width Low
Asynchronous Input Setup Time (see Note
5)
BERR Asserted to DTACK Asserted (see
Notes 2 and 3)
Data-Out Hold from Clock High
R/W Asserted to Data Bus Impedance
Change
HALT/RESET Pulse Width (see Note 4)
BGACK Negated to AS, DS, R/W Driven
BGACK Negated to FC
BR Negated to AS, DS, R/W Driven (see
Note 7)
BR Negated to FC (see Note 7)
Clock High to BCLR Asserted
Clock High to BCLR High Impedance (See
Note 10)
Clock Low (S0 Falling Edge during read) to
RMC Asserted
Clock High (during write) to RMC Negated
RMC Negated to BG Asserted (see Note 9)
Characteristic
MC68302 USER’S MANUAL
Symbol
t
t
t
t
t
t
t
GALBRH
t
t
t
t
t
GALASA
t
BELDAL
t
CHRMH
RMHGL
GALGH
SHVPH
t
t
t
t
CHBCH
GALAV
RLDBD
CHBCL
CLRML
CHDOI
HRPW
GASD
GAFD
RHSD
RHFD
t
t
t
t
GLZ
GAL
ASI
GH
Min
16.67 MHz
2.5
1.5
1.5
1.5
1.5
10
15
30
10
10
10
—
—
—
—
—
—
0
0
0
1
1
Max
4.5
1.5
50
50
30
30
30
30
30
—
—
—
—
—
—
—
—
—
—
—
—
—
Min
2.5
1.5
1.5
1.5
1.5
10
15
30
10
10
10
—
—
—
—
—
—
0
0
0
1
1
20 MHz
Electrical Characteristics
Max
4.5
1.5
42
42
25
25
25
25
25
—
—
—
—
—
—
—
—
—
—
—
—
—
Min
2.5
1.5
1.5
1.5
1.5
10
15
20
10
—
—
—
—
—
—
0
7
7
0
0
1
1
25 MHz
Max
4.5
1.5
33
33
20
20
20
20
20
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
clks
clks
clks
clks
clks
clks
clks
clks
clks
ns/
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6-7