MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 423

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

APPENDIX E
SCC PROGRAMMING REFERENCE
This appendix is intended to be used as a quick programming reference for setting up the
SCCs. Each of the following three subsections pulls together the information required to set
up an SCC to operate in HDLC mode, UART mode, or transparent mode. For detailed infor-
mation about a particular register, parameter, or function, please refer to the appropriate
subsection in Section 4 Communications Processor (CP).
E.1 HDLC PROGRAMMING REFERENCE SECTION
This subsection deals with the registers and parameters required to program an SCC for
HDLC. A generic algorithm for programming the SCC is also presented.
E.1.1 HDLC Programming Model
The programming model and memory map for the HDLC protocol is shown in Table E-1 (a).
The offsets for each SCC are given above each table. Some parameters are common to all
protocols. The HDLC parameters are shown for those entries that are protocol specific.
Table E-1 (b). depicts the general and protocol-specific parameter RAM for each SCC. The
SCC registers are shown in Table E-1 (c), and the communications processor registers are
shown in Table E-1 (d). Note that reserved bits in registers should be written as zeros.
MOTOROLA
All SCC buffer descriptor tables are shown with eight Rx BDs
and eight Tx BDs. If the DRAM refresh controller is used, then
only six Tx BDs are available for SCC2. Also, if the SCP or
SMCs are used, only four Tx BDs are available for SCC3. In
these cases, the wrap bit should be set in the last Tx BD.
MC68360 USER’S MANUAL
NOTE
E-1