MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 355

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

For proper timing of write cycles, it is important to know how much time elapses between
CS negated and the data out hold time. With a 16.67-MHz MC68302, this value is a 10-ns
minimum. Thus, on a CS-controlled RAM write cycle, the RAM required data hold time must
be <= 10 ns. For the MCM6206, it is 0 ns.
D.2 SWITCHING THE EXTERNAL ROM AND RAM USING THE MC68302
When designing with the MC68302 (or simply the M68000), one of the tasks often required
is to switch the locations of the ROM and RAM in the system. This is because the reset vec-
tor needs to be supplied from ROM; whereas, the rest of the exception vectors are normally
included in RAM so that they can be modified. The exception vector area extends from $0
to $FF.
The MC68302 makes this switch easy to perform, requiring no additional glue logic. Two
chip-select lines and a few temporary locations of the dual-port RAM are used. For this ex-
ample, 256 kbytes of EPROM and 64 kbytes of RAM are used.
D.2.1 Conditions at Reset
We physically connect CS0 to the ROM and CS1 to the RAM. After reset, the MC68302 de-
faults to having only one chip select enabled (CS0), with a base address of $0 and a range
of 8 kbytes. The ROM should be programmed with an initial set of interrupt vectors, and the
reset vector should point to some location within the first 8 k of ROM. CS1 is disabled at re-
set so the RAM cannot be accessed. Also, the base address register (BAR) in the MC68302
has not been written; therefore, the dual-port RAM and other on-chip peripherals cannot be
accessed. The status register (SR) of the M68000 core is $2700, putting the core in super-
visor mode with interrupts masked. The SR is left in this condition until the ROM and RAM
are switched.
D.2.2 First Things First
The following situation now exists:
Once the reset vector has been taken, the BAR at location $0F2 should be written to locate
the MC68302 dual-port RAM and on-chip peripheral registers in memory. In this example,
$700000 is chosen as the starting point of the 4 k block of the MC68302 internal address
space; thus, we write $0700 to BAR. BAR exists internal to the MC68302 and is easily ac-
cessed even though it overlaps memory with ROM. CS0 will not activate on accesses to the
BAR.
Now that the MC68302 can be fully accessed, the ROM and RAM chip selects can be mod-
ified. First, the option register (OR) of CS0 can be extended to include all 256 kbytes by writ-
ing the base address mask in OR0 with 11111100000b. At this time, the DTACK field may
be changed to reduce the number of wait states from six to something lower. Also, while writ-
MOTOROLA
• ROM—Begins at $0; only first 8 kbytes are valid for programming.
• RAM—Undefined.
• MC68302—Undefined (except BAR at $0F2 and SCR at $0F4).
2-1/2 clocks –data setup time–CS maximum asserted time = 150 - 7 - 40 = 103 ns.
MC68302 USER’S MANUAL
MC68302 Applications
D-5