MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 261

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

4.7.4.1 SMC1 Receive Buffer Descriptor
The CP reports information about the received byte using this (BD).
E—Empty
In GCI mode, when the IMP implements the monitor channel protocol, the IMP will wait until
this bit is set by the M68000 core before acknowledging the monitor channel data. In other
modes (transparent GCI and IDL), additional received data bytes will be discarded until the
empty bit is set by the M68000 core.
L—Last (EOM)
ER—Error Condition
MS—Data Mismatch
Bits 11–10—Reserved for future use.
AB—Received A Bit
EB—Received E Bit
Data—Data Field
MOTOROLA
This bit is valid only in GCI mode when the IMP implements the monitor channel protocol.
This bit is set when the end-of-message (EOM) indication is received on the E bit.
This bit is valid only in GCI mode when the IMP implements the monitor channel protocol
and the L bit is set. This bit is set when an error condition occurs on the monitor channel
protocol. A new byte is transmitted before the IMP acknowledges the previous byte.
This bit is valid only in GCI mode when the IMP implements the monitor channel protocol.
This bit is set when two different consecutive bytes are received and is cleared when the
last two consecutive bytes match. The IMP waits for the reception of two identical consec-
utive bytes before writing new data to the receive BD.
This bit is valid only in GCI mode when the monitor channel is in transparent mode.
This bit is valid only in GCI mode when the monitor channel is in transparent mode.
The data field contains the byte of data received by SMC1.
15
E
0 = This bit is cleared by the CP to indicate that the data byte associated with this BD
1 = This bit is set by the M68000 core to indicate that the data byte associated with this
is now available to the M68000 core.
BD is empty.
14
L
When this bit is set, the data byte is not valid.
13
ER
12
MS
11
MC68302 USER’S MANUAL
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10
NOTE
AB
9
EB
8
7
Communications Processor (CP)
DATA
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0