MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 176

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Communications Processor (CP)
4.5.11.13 UART Mode Register.
Each SCC mode register is a 16-bit, memory- mapped, read-write register that controls the
SCC operation. The term UART mode register refers to the protocol-specific bits (15–6) of
the SCC mode register when that SCC is configured as a UART. The read-write UART
mode register is cleared by reset.
TPM1–TPM0—Transmitter Parity Mode
RPM—Receiver Parity Mode
When odd parity is selected, the receiver will count the number of ones in the data word. If
the total number of ones is not an odd number, the parity bit is set to one to produce an odd
number of ones. If the receiver counts an even number of ones, an error in transmission has
occurred. Similarly, for even parity, an even number of ones must result from the calculation
performed at both ends of the line.
PEN—Parity Enable
UM1–UM0—UART Mode 1–0
4-56
TPM1
15
TMP1—TMP0 select the type of parity to be performed.
00 = Odd parity; always send an odd number of ones.
01 = Force low parity; always send a zero in the parity bit position.
10 = Even parity; always send an even number of ones.
11 = Force high parity; always send a one in the parity bit position.
0 = Odd parity
1 = Even parity
0 = No parity
1 = Parity is enabled for the transmitter and receiver as determined by the parity mode
00 = Normal UART operation. Multidrop mode is disabled for point-to-point operation
01 = In the multidrop mode, an additional address/data bit is transmitted with each
TPM0
14
bits.
and an idle-line wakeup is selected. In the idle-line wakeup mode, the UART re-
ceiver is re-enabled by an idle string of 9 to 13 consecutive ones (depending on
character length and parity mode).
character. The multidrop asynchronous modes are compatible with the Motorola
MC68681 DUART, the Motorola MC68HC11 SCI interface, and the Motorola
DSP56000 SCI interface. UM0 is also used to select the wakeup mode before en-
abling the receiver or issuing the ENTER HUNT MODE command.
Multidrop mode is enabled and an address bit wakeup is selected. In the address
bit wakeup mode, the UART receiver is re-enabled when the last data bit (the 8th
or 9th) in a character is one. This configuration means that the received character
is an address, which should be processed by all inactive processors. The IMP re-
RPM
13
PEN
12
UM1
11
UM0
10
MC68302 USER’S MANUAL
FRZ
9
CL
8
RTSM
7
SL
6
5
COMMON SCC MODE BITS
MOTOROLA
0