MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 361

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Finally:
D.3.7 Final Comments
Note that nowhere in the algorithm does RBD# or TBD# need to be read. The empty and
ready bits provide all the necessary information.
Whether receiving buffers or confirming buffers, the interrupt routines deal with all the buff-
ers they can before the interrupt routine is exited. This approach is not mandatory, but if not
all buffers are dealt with, then some provision needs to be made for getting the work done
without waiting for another interrupt.
For frame-oriented protocols such as HDLC, the user may wish to only process frames, not
buffers. In this case, the algorithm would be the same, but the interrupt mask would be set
for frame interrupts only.
D.3.8 HDLC Code Listing
The following code shows the initialization of the HDLC protocol and the implementation of
the buffer processing algorithms just described. HDLC frames are continuously transmitted
and received in the SCC loopback mode.
MOTOROLA
If the interrupt was due to a buffer being transmitted, perform the following confirm pro-
cess:
2. While (CTD -> Ready) = 0 and (CTD -> data length) > 0, do the following:
3. Clear the SCC bit in the in-service register (ISR) of the interrupt controller. This is stan-
4. Return from interrupt.
*************************** BUFFER PROCESSING CODE**************************
************************************EQU TABLE******************************
* The following three values are application dependent
BASE
INIT
INT_VEC
* Commonly used Registers and Parameters
BAR
SCR
CKCR
GIMR
IPR
/* Look at frames that have been transmitted, but not confirmed */
dard procedure.
e. Clear all status bits to zero (the default condition).
f. Set (PRD -> Empty) = 1.
g. Move PRD to point to the next BD (If the wrap bit is set, point to the first BD).
a. Check for errors in the BD.
b. Clear all status bits to zero (the default condition).
c. Clear out the data length field so that it is zero to start with. This procedure al-
d. Move CTD to point to the next BD. (If the wrap bit is set, point to the first BD.)
lows new data be placed in this transmit buffer by the transmit algorithm.
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$0700000
$0030300
$0031000
$0F2
$0F4
$0F6
BASE +
BASE +
MC68302 USER’S MANUAL
$812
$814
;This is set according to the val in BAR
;Initialization Routine
;Interrupt Vector for SCC1
;Base Address Register
;System Control Register
;Clock Control Register
;Global Interrupt Mode Register
;Interrupt Pending Register
MC68302 Applications
D-11