MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 375

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
No Action Because an Internal Transfer
DREQ, DACK, DONE Are Used To Read the
Source Portion of the Transfer
DREQ, DACK, DONE Are Used To Read the Des-
tination Portion of the Transfer
Allow Interrupt on No Error (see Notes 1, 2)
Inhibit Interrupt on No Error (see Note 2)
Allow Interrupt on Bus Error
Inhibit Interrupt on Bus Error
Internal Request Mode (see BT bits)
Internal Request Mode at Maximum Rate (Burst)
External Request Burst Transfer Mode (Note 3)
External Request Cycle Steal Mode (see Note 4)
Source Address Pointer Increment Off
Source Address Pointer Increment On
Destination Address Pointer Increment Off
Destination Address Pointer Increment On
Source Size—Reserved
Source Size = Byte
Source Size = Word
Source Size—Reserved
Destination Size—Reserved
Destination Size = Byte
Destination Size = Word
Destination Size—Reserved
IDMA Transfer of up to 75% of Bus Bandwidth
(see Note 5)
IDMA Transfer of up to 50% Of Bus Bandwidth
(see Note 5)
IDMA Transfer of up to 25% Of Bus Bandwidth
(see Note 5)
IDMA Transfer of up to 12.5% Of Bandwidth (see
Note 5)
Normal Operation (Software Reset OH)
Software Reset - Abort External Pending Cycles
Stop IDMA at the End of Current Transfer
Start (or Restart) IDMA Channel Transfer
NOTES:
1. When external pin DONE asserts, an interrupt request is generated.
2. The DONE bit is set in the CSR at the conclusion of data transfer.
3. Transfer occurs at maximum rate. Hardware signal DREQ is level sensitive.
4. Hardware signal DREQ is edge sensitive.
5. These percentages are valid only when bits 11 and 10 = 00.
Operation
Table D-2. Channel Mode Register Bits
MC68302 USER’S MANUAL
15 14 13 12 11 10
X
0
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
9
0
1
CMR Bits
8
0
1
7
0
0
1
1
6
0
1
0
1
MC68302 Applications
5
0
0
1
1
4
0
1
0
1
3
0
0
1
1
2
0
1
0
1
1
0
1
D-25
0
0
1