MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 460

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

SCC Programming Reference
E.3.1.2.6 Transparent Status Register (SCCS). This 8-bit register is located at offset
$88C (SCC1), $89C (SCC2), and $8AC (SCC3)on D15-D8 of a 16-bit data bus. The SCCS
register reflects the current status of the CD and CTS lines as seen by the SCC.
CD—Carrier Detect Status Changed (valid only when the ENR bit is set and the receive
clock is running)
CTS—Clear-To-Send Status Changed (valid only when the ENT bit is set and the transmit
clock is running)
E.3.1.3 GENERAL AND TRANSPARENT PROTOCOL-SPECIFIC PARAMETER RAM.
Each SCC has 32 words of parameter RAM used to configure receive and transmit opera-
tion, store temporary parameters for the CP, and maintain counters. The first 14 words are
general parameters, which are the same for each protocol. The last 18 words are specific to
the protocol selected. The following subsections discuss the parameters that the user must
initialize to configure the transparent operation.
E.3.1.3.1 RFCR/TFCR—Rx Function Code/Tx Function Code. This
contains the function codes of the receive data buffers and transmit data buffers. The user
must initialize the function codes (FC2-FC0) to a value less than 7.
E.3.1.3.2 MRBLR—Maximum Rx Buffer Length. This 16-bit parameter defines the maxi-
mum receiver buffer length for each of the eight receive buffer descriptors.
E.3.1.4 RECEIVE BUFFER DESCRIPTORS. Each SCC has eight receive buffer descrip-
tors. Each buffer descriptor consists of four words as shown below. Reserved bits in regis-
ters should be written as zeros.
E.3.1.4.1 Receive BD Control/Status Word. To initialize the buffer, the user should write
bits15-12 and clear bits1-0. The IMP clears bit 15 when the buffer is closed and sets bits 5-
0 depending on which error occurred.
E-38
OFFSET + 0
OFFSET +2
OFFSET +4
OFFSET +6
15
0
0 = CD is asserted.
1 = CD is not asserted.
0 = CTS is asserted.
1 = CTS is not asserted.
FC2
14
15
E
FC1
13
14
X
FC0
12
13
W
11
—
7
0
12
I
—
10
6
0
11
—
MC68360 USER’S MANUAL
—
10
5
9
0
—
—
—
9
RX BUFFER POINTER
4
8
0
DATA LENGTH
—
8
—
3
7
0
—
7
FC2
—
2
6
—
6
FC1
CD
1
5
—
5
CTS
FC0
0
4
—
4
3
0
16-bit
—
3
2
0
—
2
MOTOROLA
parameter
1
0
OV
1
CD
0
0
0