MC68302EH20C Freescale Semiconductor, MC68302EH20C Datasheet - Page 275

• Manufacturer Part Number: MC68302EH20C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH20C

• Processor Type: M683xx 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

5.9 INTERRUPT CONTROL PINS
The interrupt control pins are shown in Figure 5-9.
These inputs have dual functionality:
FC2–FC0—Function Codes 2–0
AVEC/IOUT0—Autovector Input/Interrupt Output 0
MOTOROLA
• IPL0/IRQ1
• IPL1/IRQ6
• IPL2/IRQ7—Interrupt Priority Level 2–0/Interrupt Request 1,6,7
As IPL2–IPL0 (normal mode), these input pins indicate the encoded priority level of the
external device requesting an interrupt. Level 7 is the highest (nonmaskable) priority;
whereas, level 0 indicates that no interrupt is requested. The least significant bit is IPL0,
and the most significant bit is IPL2. These lines must remain stable until the M68000 core
signals an interrupt acknowledge through FC2–FC0 and A19–A16 to ensure that the in-
terrupt is properly recognized.
As IRQ1, IRQ6, and IRQ7 (dedicated mode), these inputs indicate to the MC68302 that
an external device is requesting an interrupt. Level 7 is the highest level and cannot be
masked. Level 1 is the lowest level. Each one of these inputs (except for level 7) can be
programmed to be either level-sensitive or edge-sensitive. The M68000 always treats a
level 7 interrupt as edge sensitive.
These bidirectional signals indicate the state and the cycle type currently being executed.
The information indicated by the function code outputs is valid whenever AS is active.
These lines are outputs when the IMP (M68000 core, SDMA, or IDMA) is the bus master
and are inputs otherwise. The function codes output by the M68000 core are predefined;
whereas, those output by the SDMA and IDMA are programmable. The function code
lines are inputs to the chip-select logic and IMP internal register decoding in the BAR.
In normal operation, this signal functions as the input AVEC. AVEC, when asserted during
an interrupt acknowledge cycle, indicates that the M68000 core should use automatic
vectoring for an interrupt. This pin operates like VPA on the MC68000, but is used for au-
Figure 5-9. Interrupt Control Pins
MC68302 USER’S MANUAL
MC68302
IPL0 / IRQ1
IPL1 / IRQ6
IPL2 / IRQ7
FC0
FC1
FC2
AVEC / IOUT0
Signal Description
5-11