LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 818

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
4.5.13
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.4.1
4.6.5
4.6.6
4.6.7
4.6.8
4.6.9
4.7
4.7.1
4.7.2
Chapter 5: LPC17xx Flash accelerator
5.1
5.2
5.2.1
5.2.2
Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC)
6.1
6.2
6.3
6.4
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
UM10360
User manual
PLL1 (Phase Locked Loop 1) . . . . . . . . . . . . . 47
Clock dividers . . . . . . . . . . . . . . . . . . . . . . . . . 54
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Flash accelerator blocks . . . . . . . . . . . . . . . . . 68
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . 72
Vector table remapping . . . . . . . . . . . . . . . . . . 75
Register description . . . . . . . . . . . . . . . . . . . . 76
Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
PLL0 setup sequence . . . . . . . . . . . . . . . . . . . 46
PLL1 register description . . . . . . . . . . . . . . . . 47
PLL1 Control register (PLL1CON - 0x400F
C0A0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PLL1 Configuration register (PLL1CFG -
0x400F C0A4) . . . . . . . . . . . . . . . . . . . . . . . . 49
PLL1 Status register (PLL1STAT - 0x400F
C0A8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PLL1 modes . . . . . . . . . . . . . . . . . . . . . . . . . . 50
PLL1 Interrupt: PLOCK1. . . . . . . . . . . . . . . . . 50
PLL1 Feed register (PLL1FEED - 0x400F
C0AC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
PLL1 and Power-down mode . . . . . . . . . . . . . 51
PLL1 frequency calculation . . . . . . . . . . . . . . 52
Procedure for determining PLL1 settings . . . . 52
CPU Clock Configuration register (CCLKCFG -
0x400F C104) . . . . . . . . . . . . . . . . . . . . . . . . . 54
USB Clock Configuration register (USBCLKCFG -
0x400F C108) . . . . . . . . . . . . . . . . . . . . . . . . . 55
Flash memory bank . . . . . . . . . . . . . . . . . . . . 68
Flash programming Issues . . . . . . . . . . . . . . . 69
Examples: . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
0xE000 E100) . . . . . . . . . . . . . . . . . . . . . . . . . 77
0xE000 E104) . . . . . . . . . . . . . . . . . . . . . . . . . 78
Interrupt Clear-Enable Register 0 (ICER0 -
0xE000 E180) . . . . . . . . . . . . . . . . . . . . . . . . . 79
Interrupt Clear-Enable Register 1 register (ICER1
- 0xE000 E184). . . . . . . . . . . . . . . . . . . . . . . . 80
Interrupt Set-Pending Register 0 register (ISPR0 -
0xE000 E200) . . . . . . . . . . . . . . . . . . . . . . . . . 81
Interrupt Set-Enable Register 0 register (ISER0 -
Interrupt Set-Enable Register 1 register (ISER1 -
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
4.7.3
4.8
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
4.8.7
4.8.7.1
4.8.8
4.8.9
4.8.10
4.8.11
4.9
4.10
4.10.1
5.3
5.4
5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.5.10
6.5.11
6.5.12
6.5.13
Power control . . . . . . . . . . . . . . . . . . . . . . . . . 58
Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . . 65
External clock output pin . . . . . . . . . . . . . . . . 66
Register description . . . . . . . . . . . . . . . . . . . . 69
Flash Accelerator Configuration register
(FLASHCFG - 0x400F C000) . . . . . . . . . . . . . . 70
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Peripheral Clock Selection registers 0 and 1
(PCLKSEL0 - 0x400F C1A8 and PCLKSEL1 -
0x400F C1AC) . . . . . . . . . . . . . . . . . . . . . . . . 56
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Deep Sleep mode . . . . . . . . . . . . . . . . . . . . . 58
Power-down mode . . . . . . . . . . . . . . . . . . . . . 59
Deep Power-down mode . . . . . . . . . . . . . . . . 60
Peripheral power control . . . . . . . . . . . . . . . . 60
Register description . . . . . . . . . . . . . . . . . . . . 60
Power Mode Control register (PCON -
0x400F C0C0) . . . . . . . . . . . . . . . . . . . . . . . . 61
Encoding of Reduced Power Modes . . . . . . . 62
Wake-up from Reduced Power Modes . . . . . 62
Power Control for Peripherals register (PCONP -
0x400F C0C4) . . . . . . . . . . . . . . . . . . . . . . . . 62
Power control usage notes . . . . . . . . . . . . . . 64
Power domains . . . . . . . . . . . . . . . . . . . . . . . 64
Clock Output Configuration register
(CLKOUTCFG - 0x400F C1C8) . . . . . . . . . . . 66
Interrupt Set-Pending Register 1 register (ISPR1 -
0xE000 E204) . . . . . . . . . . . . . . . . . . . . . . . . 82
(ICPR0 - 0xE000 E280) . . . . . . . . . . . . . . . . . 83
(ICPR1 - 0xE000 E284) . . . . . . . . . . . . . . . . . 84
Interrupt Active Bit Register 0 (IABR0 - 0xE000
E300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Interrupt Active Bit Register 1 (IABR1 - 0xE000
E304) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Interrupt Priority Register 0 (IPR0 - 0xE000
E400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Interrupt Priority Register 1 (IPR1 - 0xE000
E404) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Interrupt Priority Register 2 (IPR2 - 0xE000
E408) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
. . . . . Interrupt Clear-Pending Register 0 register
. . . . . Interrupt Clear-Pending Register 1 register
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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