LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 791

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
34.4.5.5.1 SIZE field values
Table 685. RASR bit assignments
For information about access permission, see
The SIZE field defines the size of the MPU memory region specified by the RNR. as
follows:
The smallest permitted region size is 32B, corresponding to a SIZE value of 4.
gives example SIZE values, with the corresponding region size and value of N in the
RBAR.
Table 686. Example SIZE field values
[1]
Bits
[31:29]
[28]
[27]
[26:24]
[23:22]
[21:19, 17, 16]
[18]
[15:8]
[7:6]
[5:1]
[0]
SIZE value
b00100 (4)
b01001 (9)
b10011 (19)
b11101 (29)
b11111 (31)
(Region size in bytes) = 2
In the RBAR, see
All information provided in this document is subject to legal disclaimers.
Name
-
XN
-
AP
-
TEX, C, B
S
SRD
-
SIZE
ENABLE
Table
Rev. 2 — 19 August 2010
Region size
32B
1KB
1MB
1GB
4GB
684.
Function
Reserved.
Instruction access disable bit:
0 = instruction fetches enabled
1 = instruction fetches disabled.
Reserved.
Access permission field, see
Reserved.
Memory access attributes, see
Shareable bit, see
Subregion disable bits. For each bit in this field:
0 = corresponding sub-region is enabled
1 = corresponding sub-region is disabled
See
Region sizes of 128 bytes and less do not support subregions.
When writing the attributes for such a region, write the SRD field as
0x00 .
Reserved.
Specifies the size of the MPU protection region. The minimum
permitted value is 3 (b00010), see See
information.
Region enable bit.
(SIZE+1)
Section 34.4.5.8.3
Chapter 34: Appendix: Cortex-M3 user guide
Table
Value of N
5
10
20
30
b01100
Section
for more information.
687.
Table
34.4.5.6.
[1]
Table
689.
687.
Section 34.4.5.5.1
Note
Minimum permitted
size
-
-
-
Maximum possible size
UM10360
© NXP B.V. 2010. All rights reserved.
Table 686
for more
791 of 840