LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 152

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 131. Pad operation
Table 132. Back-to-back Inter-packet-gap register (IPGT - address 0x5000 0008) bit description
Table 133. Non Back-to-back Inter-packet-gap register (IPGR - address 0x5000 000C) bit description
UM10360
User manual
Type
Any
Any
Any
Any
Bit
6:0
31:7
Bit
6:0
7
14:8
31:15 -
Symbol
NON-BACK-TO-BACK
INTER-PACKET-GAP PART2
-
NON-BACK-TO-BACK
INTER-PACKET-GAP PART1
Symbol
BACK-TO-BACK
INTER-PACKET-GAP
-
Auto detect
pad enable
MAC2 [7]
x
0
x
1
10.11.3 Back-to-Back Inter-Packet-Gap Register (IPGT - 0x5000 0008)
10.11.4 Non Back-to-Back Inter-Packet-Gap Register (IPGR - 0x5000 000C)
VLAN pad
enable
MAC2 [6]
x
0
1
0
The Back-to-Back Inter-Packet-Gap register (IPGT) has an address of 0x5000 0008. Its
bit definition is shown in
The Non Back-to-Back Inter-Packet-Gap register (IPGR) has an address of 0x5000 000C.
Its bit definition is shown in
Function
This is a programmable field representing the nibble time offset of the minimum
possible period between the end of any transmitted packet to the beginning of the
next. In Full-Duplex mode, the register value should be the desired period in
nibble times minus 3. In Half-Duplex mode, the register value should be the
desired period in nibble times minus 6. In Full-Duplex the recommended setting is
0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or
9.6 µs (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d),
which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs
(in 10 Mbps mode).
Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Pad/CRC
enable
MAC2 [5]
0
1
1
1
Function
This is a programmable field representing the Non-Back-to-Back
Inter-Packet-Gap. The recommended value is 0x12 (18d), which
represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs (in
10 Mbps mode).
Reserved. User software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
This is a programmable field representing the optional carrierSense
window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is
detected during the timing of IPGR1, the MAC defers to carrier. If,
however, carrier becomes active after IPGR1, the MAC continues timing
IPGR2 and transmits, knowingly causing a collision, thus ensuring fair
access to medium. Its range of values is 0x0 to IPGR2. The recommended
value is 0xC (12d)
Reserved. User software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Action
No pad or CRC check
Pad to 60 bytes, append CRC
Pad to 64 bytes, append CRC
If untagged, pad to 60 bytes and append CRC. If VLAN tagged: pad to
64 bytes and append CRC.
Table
Table
132.
133.
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
152 of 840
Reset
value
0x0
0x0
Reset
value
0x0
0x0
0x0
0x0