LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 304

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 277: UARTn Interrupt Handling
UM10360
User manual
U0IIR[3:0]
value
0001
0110
0100
1100
0010
[1]
Priority Interrupt
-
Highest
Second
Second
Third
Type
None
RX Line
Status / Error
RX Data
Available
Character
Time-out
indication
THRE
The UARTn RLS interrupt (UnIIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UARTn Rx input: overrun error
(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UARTn Rx error
condition that set the interrupt can be observed via U0LSR[4:1]. The interrupt is cleared
upon an UnLSR read.
The UARTn RDA interrupt (UnIIR[3:1] = 010) shares the second level priority with the CTI
interrupt (UnIIR[3:1] = 110). The RDA is activated when the UARTn Rx FIFO reaches the
trigger level defined in UnFCR[7:6] and is reset when the UARTn Rx FIFO depth falls
below the trigger level. When the RDA interrupt goes active, the CPU can read a block of
data defined by the trigger level.
The CTI interrupt (UnIIR[3:1] = 110) is a second level interrupt and is set when the UARTn
Rx FIFO contains at least one character and no UARTn Rx FIFO activity has occurred in
3.5 to 4.5 character times. Any UARTn Rx FIFO activity (read or write of UARTn RSR) will
clear the interrupt. This interrupt is intended to flush the UARTn RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripheral
wished to send a 105 character message and the trigger level was 10 characters, the
CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5
CTI interrupts (depending on the service routine) resulting in the transfer of the remaining
5 characters.
[1]
[2]
[3]
[4]
The UARTn THRE interrupt (UnIIR[3:1] = 001) is a third level interrupt and is activated
when the UARTn THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UARTn THR FIFO a chance to
Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
For details see
0x4009 8014, U3LSR - 0x4009 C014)”
For details see
0x4009 8000, U3RBR - 0x4009 C000 when DLAB = 0)”
For details see
0x4009 8008, U3IIR - 0x4009 C008)”
0x4000 C000, U2THR - 0x4009 8000, U3THR - 0x4009 C000 when DLAB = 0)”
Interrupt Source
None
OE
Rx data available or trigger level reached in FIFO
(UnFCR0=1)
Minimum of one character in the Rx FIFO and no
character input or removed during a time period
depending on how many characters are in FIFO and
what the trigger level is set at (3.5 to 4.5 character
times).
The exact time will be:
[(word length) × 7 - 2] × 8 + [(trigger level - number of
characters) × 8 + 1] RCLKs
THRE
[2]
All information provided in this document is subject to legal disclaimers.
Section 14.4.8 “UARTn Line Status Register (U0LSR - 0x4000 C014, U2LSR -
Section 14.4.1 “UARTn Receiver Buffer Register (U0RBR - 0x4000 C000, U2RBR -
Section 14.4.5 “UARTn Interrupt Identification Register (U0IIR - 0x4000 C008, U2IIR -
or PE
[2]
[2]
Rev. 2 — 19 August 2010
or FE
[2]
or BI
and
[2]
Section 14.4.2 “UARTn Transmit Holding Register (U0THR -
Chapter 14: LPC17xx UART0/2/3
Interrupt Reset
-
UnLSR Read
UnRBR Read
FIFO drops below trigger level
UnRBR Read
UnIIR Read (if source of
interrupt) or THR write
UM10360
© NXP B.V. 2010. All rights reserved.
[2]
[3]
[3]
or UARTn
304 of 840
[4]