LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 205

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
10.17.15 Huge frames and frame length checking
10.17.16 Statistics counters
10.17.17 MAC status vectors
If EPADEN is 1, then small frames will be padded and a CRC will always be added to the
padded frames. In this case if ADPEN and VLPEN are both 0, then the frames will be
padded to 60 bytes and a CRC will be added creating 64 bytes frames; if VLPEN is 1, the
frames will be padded to 64 bytes and a CRC will be added creating 68 bytes frames; if
ADPEN is 1, while VLPEN is 0 VLAN frames will be padded to 64 bytes, non VLAN
frames will be padded to 60 bytes, and a CRC will be added to padded frames, creating
64 or 68 bytes padded frames.
If CRC generation is enabled, CRC generation can be delayed by four bytes by setting the
DELAYED CRC bit in the MAC2 register, in order to skip proprietary header information.
The ‘HUGE FRAME ENABLE’ bit in the MAC2 configuration register can be set to 1 to
enable transmission and reception of frames of any length. Huge frame transmission can
be enabled on a per frame basis by setting the Override and Huge bits in the transmit
descriptor Control word.
When enabling huge frames, the Ethernet block will not check frame lengths and report
frame length errors (RangeError and LengthError). If huge frames are enabled, the
received byte count in the RSV register may be invalid because the frame may exceed the
maximum size; the RxSize fields from the receive status arrays will be valid.
Frame lengths are checked by comparing the length/type field of the frame to the actual
number of bytes in the frame. A LengthError is reported by setting the corresponding bit in
the receive StatusInfo word.
The MAXF register allows the device driver to specify the maximum number of bytes in a
frame. The Ethernet block will compare the actual receive frame to the MAXF value and
report a RangeError in the receive StatusInfo word if the frame is larger.
Generally, Ethernet applications maintain many counters that track Ethernet traffic
statistics. There are a number of standards specifying such counters, such as IEEE std
802.3 / clause 30. Other standards are RFC 2665 and RFC 2233.
The approach taken here is that by default all counters are implemented in software. With
the help of the StatusInfo field in frame statuses, many of the important statistics events
listed in the standards can be counted by software.
Transmit and receive status information as detected by the MAC are available in registers
TSV0, TSV1 and RSV so that software can poll them. These registers are normally of
limited use because the communication between driver software and the Ethernet block
takes place primarily through frame descriptors. Statistical events can be counted by
software in the device driver. However, for debug purposes the transmit and receive status
vectors are made visible. They are valid as long as the internal status of the MAC is valid
and should typically only be read when the transmit and receive processes are halted.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
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