LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 735

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
34.3.1.5 Data types
34.3.1.6 The Cortex Microcontroller Software Interface Standard
The NVIC registers control interrupt handling. See
Interrupt Controller”
The processor:
For a Cortex-M3 microcontroller system, the Cortex Microcontroller Software Interface
Standard (CMSIS) defines:
The CMSIS includes address definitions and data structures for the core peripherals in the
Cortex-M3 processor. It also includes optional interfaces for middleware components
comprising a TCP/IP stack and a Flash file system.
CMSIS simplifies software development by enabling the reuse of template code and the
combination of CMSIS-compliant software components from various middleware vendors.
Software vendors can expand the CMSIS to include their peripheral definitions and
access functions for those peripherals.
This document includes the register names defined by the CMSIS, and gives short
descriptions of the CMSIS functions that address the processor core and the core
peripherals.
Remark: This document uses the register short names defined by the CMSIS. In a few
cases these differ from the architectural short names that might be used in other
documents.
The following sections give more information about the CMSIS:
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supports the following data types:
– 32-bit words
– 16-bit halfwords
– 8-bit bytes
supports 64-bit data transfer instructions.
manages all data memory accesses as little-endian. See
information.
a common way to:
– access peripheral registers
– define exception vectors
the names of:
– the registers of the core peripherals
– the core exception vectors
a device-independent interface for RTOS kernels, including a debug channel.
Section 34.3.5.4
Section 34.2.2 “Intrinsic functions”
Section 34.4.2.1 “The CMSIS mapping of the Cortex-M3 NVIC registers”
All information provided in this document is subject to legal disclaimers.
for more information.
Rev. 2 — 19 August 2010
Chapter 34: Appendix: Cortex-M3 user guide
Section 34.4.2 “Nested Vectored
Section 34.3.2.1
UM10360
© NXP B.V. 2010. All rights reserved.
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