LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 481

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
Table 414: Receive Clock Rate register (I2SRXRATE - address 0x400A 8024) bit description
Table 415: Transmit Clock Rate register (I2TXBITRATE - address 0x400A 8028) bit description
Table 416: Receive Clock Rate register (I2SRXBITRATE - address 0x400A 802C) bit description
UM10360
User manual
Bit
7:0
15:8
31:16
Bit
5:0
31:6
Bit
5:0
31:6
Symbol
Y_divider
X_divider
-
Symbol
tx_bitrate
-
Symbol
rx_bitrate
-
20.5.12 Receive Clock Bit Rate register (I2SRXBITRATE - 0x400A 802C)
20.5.13 Transmit Mode Control register (I2STXMODE - 0x400A 8030)
20.5.11 Transmit Clock Bit Rate register (I2STXBITRATE - 0x400A 8028)
Description
I
receive
0 stops the clock.
I
receive
range of possibilities. Note: the resulting ratio X/Y is divided by 2.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Description
I
clock.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Description
I
clock.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
2
2
2
2
S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit
S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit
S receive
S receive
The bit rate for the I
register. The value depends on the audio sample rate desired, and the data size and
format (stereo/mono) used. For example, a 48 kHz sample rate for 16-bit stereo data
requires a bit rate of 48,000×16×2 = 1.536 MHz.
The bit rate for the I
The value depends on the audio sample rate, as well as the data size and format used.
The calculation is the same as for I2SRXBITRATE.
The Transmit Mode Control register contains additional controls for transmit clock source,
enabling the 4-pin mode, and how MCLK is used. See
useful mode combinations.
MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of
MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide
MCLK rate denominator. This value is used to divide PCLK to produce the
MCLK rate numerator. This value is used to multiply PCLK by to produce the
All information provided in this document is subject to legal disclaimers.
2
2
S receiver is determined by the value of the I2SRXBITRATE register.
S transmitter is determined by the value of the I2STXBITRATE
Rev. 2 — 19 August 2010
Section 20.7
Chapter 20: LPC17xx I2S
for a summary of
UM10360
© NXP B.V. 2010. All rights reserved.
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Reset
Value
0
0
NA
Reset
Value
0
NA
Reset
Value
0
NA