LPC1759FBD80,551 NXP Semiconductors, LPC1759FBD80,551 Datasheet - Page 288

• Manufacturer Part Number: LPC1759FBD80,551
• Description: IC ARM CORTEX MCU 512K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1759FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC17xx
• Maximum Speed: 120 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4968; 935290523551

NXP Semiconductors
UM10360
User manual
Fig 40. Hardware support for B-device switching from peripheral state to host state
drive J on internal host controller port
yes
connect from A-device detected?
set HNP_SUCCESS
set PORT_FUNC[0]
and SE0 on U1
Figure 41
hardware actions setting REMOVE_PU, HNP_SUCCESS, AND HNP_FAILURE. The
relationship of the software actions to the Dual-Role B-Device states is also shown.
B-device states are in bold font with a circle around them.
yes
no
no
no
disconnect device controller from U1
wait 25 μs for bus to settle
shows the actions that the OTG software stack should take in response to the
bus reset/resume detected?
B_HNP_TRACK = 1 ?
B_HNP_TRACK = 0
set REMOVE_PU
PU_REMOVED set?
bus suspended ?
All information provided in this document is subject to legal disclaimers.
idle
no
Rev. 2 — 19 August 2010
no
SE0 sent by host?
bus reset/resume detected?
yes
no
no
yes
reconnect port U1 to the
clear B_HNP_TRACK,
clear PU_REMOVED
set HNP_FAILURE,
PU_REMOVED set?
device controller
Chapter 13: LPC17xx USB OTG
connect U1 to host controller
clear B_HNP_TRACK
clear PU_REMOVED
yes
reconnect port U1 to the
device controller
UM10360
© NXP B.V. 2010. All rights reserved.
288 of 840